CF52012 datasheet(41/48 Pages) INTEL

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Symbol

Parameter

Min

Typical

Max

Unit

DCLK

high time for EPCQ512/A

3.375

—

tCL(19)

DCLK

low time for all devices except

EPCQ512/A

—

DCLK

low time for EPCQ512/A

3.375

—

tNCSSU

Chip select (nCS) setup time for all devices

except EPCQ512/A

—

DCLK

low time for EPCQ512/A

3.375

—

tNCSH

Chip select (nCS) hold time for all devices

except EPCQ512/A

—

Chip select (nCS) hold time for EPCQ512/A

3.375

—

tDSU

DATA[]

in setup time before the rising edge on

DCLK

for all devices except EPCQ512/A

—

DATA[]

in setup time before the rising edge on

DCLK

for EPCQ512/A

1.75

—

tDH

DATA[]

hold time after the rising edge on

DCLK

for all devices except EPCQ512/A

—

DATA[]

hold time after the rising edge on

DCLK

for EPCQ512/A

2.5

—

tCSH

Chip select (nCS) high time

—

tWB(20)

Write bytes cycle time

—

0.6

tWS(20)

Write status cycle time

—

1.3

tEB(20)

Erase bulk cycle time for EPCQ16

—

Erase bulk cycle time for EPCQ32

Erase bulk cycle time for EPCQ64

250

Erase bulk cycle time for EPCQ128

170

250

Erase bulk cycle time for EPCQ256

240

480

Erase bulk cycle time for EPCQ512/A

153

460

tES(20)

Erase sector cycle time for all devices except

EPCQ512/A

—

0.7

Erase sector cycle time for EPCQ512/A

0.15

tESS (20)

Erase subsector cycle time for all devices

except EPCQ512/A

—

0.3

1.5

Erase subsector cycle time for EPCQ512/A

0.05

0.4

(19) The value must be larger /than or equal to 1/f WCLK.

(20) The Write Operation Timing Diagram does not show these parameters.

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 Datasheet(PDF) 41 Page - Intel Corporation

CF52012 Datasheet(HTML) 41 Page - Intel Corporation

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