CF52012 datasheet(34/48 Pages) INTEL

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Figure 12.

Extended Dual Input Fast Read Operation Timing Diagram

To access the entire EPCQ256 or EPCQ512/A memory, use 4-byte addressing mode. In the 4-byte addressing

mode, the address width is 32-bit address.

9 10 11 12 13 14 15 16 17 18 19 20

22 20 18 16 14 12 10

23 21 19 17 15 13 11

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Operation Code (BBh)

Dummy Clock Cycles

Byte 1

Byte 2

Byte 3

Byte 4

nCS

DCLK

DATA0

DATA1

nCS

DCLK

DATA0

DATA1

24-Bit Address

I/O switches from Input to Output

1.7.7. Extended Quad Input Fast Read Operation (EBh)

This operation is similar to the extended dual input fast read operation except that the

data and addresses are shifted in and out on the DATA0, DATA1, DATA2, and DATA3

pins.

Figure 13.

Extended Quad Input Fast Read Operation

To access the entire EPCQ256 or EPCQ512/A memory, use 4-byte addressing mode. In the 4-byte addressing

mode, the address width is 32-bit address.

11 12 13 14

DATA0

DCLK

Operating Code (EBh)

15 16

17 18 19

4 0

20 16 12 8

5 1

21 17 13 9

DATA1

High Impedance

Byte 1

7 3

23 19 15 11

6 2

22 18 14 10

DATA2

High Impedance

Byte 2

6 Dummy Clock Cycles

24 Bit Address

DATA3

I/O Switches from Input to Output

4 5

8 9

4 0 4 0

5 1 5 1

6 2 6 2

7 3 7 3

nCS

1.7.8. Read Device Identification Operation (9Fh)

This operation reads the 8-bit device identification of the EPCQ device from the DATA1

output pin. If this operation is shifted in while an erase or write cycle is in progress,

the operation is not executed and does not affect the erase or write cycle in progress.

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

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