CF52012 datasheet(38/48 Pages) INTEL

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Figure 19.

Erase Bulk Operation Timing Diagram

Operation Code (C7h)

DATA0

nCS

DCLK

The device initiates a self-timed erase bulk cycle immediately after the nCS signal is

driven high. For details about the self-timed erase bulk cycle time, refer to tEB in the

related information below.

You must account for this delay before accessing the memory contents. Alternatively,

you can check the write in progress bit in the status register by executing the read

status operation while the self-timed erase cycle is in progress. The write in progress

bit is set to 1 during the self-timed erase cycle and 0 when it is complete. The write

enable latch bit in the status register is reset to 0 before the erase cycle is complete.

Related Information

Write Operation Timing on page 40

The Write Operation Parameters provides more information about tWS, tES and tWB.

1.7.13. Erase Sector Operation (D8h)

The erase sector operation allows you to erase a certain sector in the EPCQ device by

setting all the bits inside the sector to 1 or 0xFF. This operation is useful if you want

to access the unused sectors as a general purpose memory in your applications. You

must execute the write enable operation before the erase sector operation.

When you execute the erase sector operation, you must first shift in the erase sector

operation code, followed by the 3-byte addressing mode (A[23..0]) or the 4-byte

addressing mode (A[31..0]) of the chosen sector on the DATA0 pin. The 3-byte

addressing mode or the 4-byte addressing mode for the erase sector operation can be

any address inside the specified sector. Drive the nCS signal high after the eighth bit

of the erase sector operation code has been latched in.

Figure 20.

Erase Sector Operation Timing Diagram

To access the entire EPCQ256 or EPCQ512/A memory, use 4-byte addressing mode. In the 4-byte addressing

mode, the address width is 32-bit address.

DATA0

Operation Code (D8h)

24-Bit Address

nCS

DCLK

28 29 30 31

23 22

MSB

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

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