CF52012 datasheet(27/48 Pages) INTEL

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1.6.3. Non-Volatile Configuration Register

Table 28.

Dummy Clock Cycles and Address Bytes for the Non-Volatile Configuration

FPGA Device

Dummy Clock Cycles

AS x1

AS x4

• Arria® GX

• Arria II

• Cyclone®

• Cyclone II

• Cyclone III

• Cyclone IV

• Stratix®

• Stratix GX

• Stratix II

• Stratix II GX

• Stratix III

• Stratix IV

• Intel Cyclone 10 LP

—

Table 29.

Dummy Clock Cycles and Address Bytes for the Non-Volatile Configuration

FPGA Device

Address Bytes(12)

Dummy Clock Cycles

AS x1

AS x4

• Arria V

• Cyclone V

• Stratix V

3-byte addressing

4-byte addressing

Table 30.

Non-Volatile Configuration Register Operation Bit Definition

Bit

Description

Default Value

15:12

Number of dummy clock cycles. When this number is from 0001 to 1110, the

dummy clock cycles is from 1 to 14.

0000

or 1111 (13)

11:5

Set these bits to 1111111.

1111111

Don't care.

3:1

Set these bits to 111.

111

Address byte setting.

• 0—4-byte addressing

• 1—3-byte addressing

(12) The 4-byte addressing mode is used for EPCQ256 and EPCQ512/A devices.

(13) The default dummy clock cycles is 10 for extended quad input fast read and 8 for extended

dual input fast and standard fast read.

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

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