CF52012 datasheet(32/48 Pages) INTEL

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Figure 9.

Write Disable Operation Timing Diagram

Operation Code (04h)

DATA0

nCS

DCLK

DATA[3:1]

High Impedance

1.7.4. Read Bytes Operation (03h)

When you execute the read bytes operation, you first shift in the read bytes operation

code, followed by a 3-byte addressing mode (A[23..0]) or a 4-byte addressing mode

(A[31..0]). Each address bit must be latched in on the rising edge of the DCLK

signal. After the address is latched in, the memory contents of the specified address

are shifted out serially on the DATA1 pin, beginning with the MSB. For reading Raw

Programming Data File (.rpd), the content is shifted out serially beginning with the

LSB. Each data bit is shifted out on the falling edge of the DCLK signal. The maximum

DCLK

frequency during the read bytes operation is 50 MHz.

Figure 10.

Read Bytes Operation Timing Diagram

To access the entire EPCQ256 or EPCQ512/A memory, use 4-byte addressing mode. In the 4-byte addressing

mode, the address width is 32-bit address.

nCS

DCLK

DATA0

DATA1

28 29 30 31 32 33 34 35 36 37 38 39

Operation Code (03h)

24-Bit Address

23 22 21

MSB

High Impedance

DATA Out 1

DATA Out 2

The first byte address can be at any location. The device automatically increases the

address to the next higher address after shifting out each byte of data. Therefore, the

device can read the whole memory with a single read bytes operation. When the

device reaches the highest address, the address counter restarts at 0x000000,

allowing the memory contents to be read out indefinitely until the read bytes

operation is terminated by driving the nCS signal high. If the read bytes operation is

shifted in while a write or erase cycle is in progress, the operation is not executed and

does not affect the write or erase cycle in progress.

Related Information

Write Operation Timing on page 40

The Write Operation Parameters provides more information about tWS, tES and tWB.

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

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