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ASX340 Datasheet(PDF) 74 Page - List of Unclassifed Manufacturers

Part # ASX340
Description  1/4-Inch Color NTSC/PAL Digital Image SOC with Overlay Processor
PDF  78 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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ASX340 Datasheet(HTML) 74 Page - List of Unclassifed Manufacturers

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PDF: 171981479/Source: 8304342517
Aptina reserves the right to change products or specifications without notice.
ASX340/MT9V139_DS Rev. C Pub. 3/11 EN
74
© 2010 Aptina Imaging Corporation All rights reserved.
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Aptina Confidential and Proprietary
Preliminary
Two-Wire Serial Bus Timing
Figure 55 and Table 51 describe the timing for the two-wire serial interface.
Figure 55:
Two-Wire Serial Bus Timing Parameters
Table 51:
Two-Wire Serial Bus Characteristics
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C
Parameter
Symbol
Standard-Mode
Fast-Mode
Unit
Min
Max
Min
Max
SCLK Clock Frequency
fSCL
0
100
0
400
KHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
tHD;STA
4.0
-
0.6
-
μS
LOW period of the SCLK clock
tLOW
4.7
-
1.3
-
μS
HIGH period of the SCLK clock
tHIGH
4.0
-
0.6
-
μS
Set-up time for a repeated START
condition
tSU;STA
4.7
-
0.6
-
μS
Data hold time:
tHD;DAT
04
3.455
06
0.95
μS
Data set-up time
tSU;DAT
250
-
1006
-nS
Rise time of both SDATA and SCLK signals
tr
-
1000
20 + 0.1Cb7
300
nS
Fall time of both SDATA and SCLK signals
tf
-
300
20 + 0.1Cb7
300
nS
Set-up time for STOP condition
tSU;STO
4.0
-
0.6
-
μS
SCLK
SDATA
SCLK
SDATA
Write Start
Ack
Stop
Read Start
Ack
t
SHAR
t
AHSR
t
SDHR
t
SDSR
Read Sequence
Write Sequence
Read
Address
Bit 7
Read
Address
Bit 0
Register
Value
Bit 7
Register
Value
Bit 0
Write
Address
Bit 7
Write
Address
Bit 0
Register
Value
Bit 7
Register
Value
Bit 0
t
SRTH
t
SCLK
t
STPS
t
SDH
t
SDS
t
SHAW
t
AHSW
t
STPH



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