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Z86C34 Datasheet(PDF) 56 Page - Zilog, Inc.

Part # Z86C34
Description  CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY
PDF  70 Pages
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z86C34 Datasheet(HTML) 56 Page - Zilog, Inc.

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Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
56
P R E L I M I N A R Y
DS007601-Z8X0499
ASCI STATUS REGISTER (STAT) (Continued)
Table 27. Baud Rate List (BRG Mode = 0)
Prescaler
Sampling
Rate
Baud Rate
General
Divide Ratio
Example Baud Rate (bps)
PS
Divide
Ratio
DR
Rate
SS2
SS1
SS0
Divide
Ratio
SCLK =
6.144
MHz
SCLK =
4.608
MHz
SCLK =
3.072
MHz
0
SCLK
÷ 10
016
0
0
0
÷1
SCLK ÷ 160
38400
19200
0
0
1
÷2
SCLK ÷ 320
19200
9600
0
1
0
÷4
SCLK ÷ 640
9600
4800
0
1
1
÷8
SCLK ÷ 1280
4800
2400
1
0
0
÷16
SCLK ÷ 2560
2400
1200
1
0
1
÷32
SCLK ÷ 5120
1200
600
1
1
0
÷64
SCLK ÷ 10240
600
300
164
0
0
0
÷1
SCLK ÷ 640
9600
4800
0
0
1
÷2
SCLK ÷ 1280
4800
2400
0
1
0
÷4
SCLK ÷ 2560
2400
1200
0
1
1
÷8
SCLK ÷ 5120
1200
600
1
0
0
÷16
SCLK ÷ 10240
600
300
1
0
1
÷32
SCLK ÷ 20480
300
150
1
1
0
÷64
SCLK ÷ 40960
150
75
1
SCLK
÷ 30
016
0
0
0
÷1
SCLK ÷ 480
4800
0
0
1
÷2
SCLK ÷ 960
2400
0
1
0
÷4
SCLK ÷ 1920
1200
0
1
1
÷8
SCLK ÷ 3840
600
1
0
0
÷16
SCLK ÷ 7680
300
1
0
1
÷32
SCLK ÷ 15360
150
1
1
0
÷64
SCLK ÷ 30720
75
164
0
0
0
÷1
SCLK ÷ 1920
2400
0
0
1
÷2
SCLK ÷ 3840
1200
0
1
0
÷4
SCLK ÷ 7680
600
0
1
1
÷8
SCLK ÷ 15360
300
1
0
0
÷16
SCLK ÷ 30720
150
1
0
1
÷32
SCLK ÷ 61440
75
1
1
0
÷64
SCLK ÷ 122880
37.5



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