 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
NT5CB128M8GP-EKB Datasheet(PDF) 140 Page - Nanya Technology Corporation. |
|
|
|||||||||||||||||||||||||||||
NT5CB128M8GP-EKB Datasheet(HTML) 140 Page - Nanya Technology Corporation. |
|
|
140 / 160 page  Version 2.2 140 Nanya Technology Cooperation © 04/2019 All Rights Reserved. NTC Proprietary Level: Property DDR3(L) 1Gb SDRAM NT5CB(C)128M8GN / NT5CB(C)64M16GP Parameter Symbol DDR3-800 DDR3(L)-1066 DDR3(L)-1333 Unit Min. Max. Min. Max. Min. Max. Command and Address Timing DLL locking time tDLLK 512 - 512 - 512 - nCK Internal READ Command to PRECHARGE Command delay tRTP tRTPmin.: max(4tCK, 7.5ns) tRTPmax.: - Delay from start of internal write transaction to internal read command tWTR tWTRmin.: max(4tCK, 7.5ns) tWTRmax.: - WRITE recovery time tWR 15 - 15 - 15 - ns Mode Register Set command cycle time tMRD 4 - 4 - 4 - nCK Mode Register Set command update delay tMOD tMODmin.: max(12tCK, 15ns) tMODmax.: ACT to internal read or write delay time tRCD Refer to “FundamentalAC Specifications” PRE command period tRP ACT to ACT or REF command period tRC ACTIVE to PRECHARGE command period tRAS A to A command delay tCCD 4 - 4 - 4 - nCK Auto precharge write recovery + precharge time tDAL(MIN) WR + roundup(tRP / tCK(avg)) nCK Multi-Purpose Register Recovery Time tMPRR 1 - 1 - 1 - nCK ACTIVE to ACTIVE command period (1KB page size) tRRD max(4tCK ,10ns) - max(4tCK ,7.5ns) - max(4tCK ,6ns) - ACTIVE to ACTIVE command period (2KB page size) tRRD max(4tCK ,10ns) - max(4tCK ,10ns) - max(4tCK ,7.5ns) - Four activate window (1KB page size) tFAW 40 - 37.5 - 30 - ns Four activate window (2KB page size) tFAW 50 - 50 - 45 - ns Command and Address setup time to CK, referenced to Vih(ac) / Vil(ac) levels tIS(BASE) DDR3-AC175 200 - 125 - 65 - ps tIS(BASE) DDR3-AC150 350 - 275 - 190 - ps tIS(BASE) DDR3L-AC160 215 - 140 - 80 - ps tIS(BASE) DDR3L-AC135 365 - 290 - 205 - ps Command and Address hold time from CK, referenced to Vih(dc) / Vil(dc) levels tIH(BASE) DDR3-DC100 275 - 200 - 140 - ps tIH(BASE) DDR3L-DC90 285 - 210 - 150 - ps Control and Address Input pulse width for each input tIPW 900 - 780 - 620 - ps Calibration Timing Power-up and RESET calibration time tZQINIT tZQINITmin: max(512tCK, 640ns) tZQINITmax: - Normal operation Full calibration time tZQOPER tZQOPERmin: max(256tCK, 320ns) tZQOPERmax: - Normal operation Short calibration time tZQCS tZQCSmin: max(64 tCK, 80ns) tZQCSmax: - Reset Timing Exit Reset from CKE HIGH to a valid command tXPR tXPRmin.: max(5 tCK, tRFC(min) + 10ns) tXPRmax.: - Self Refresh Timings Exit Self Refresh to commands not requiring a locked DLL tXS tXSmin.: max(5 tCK, tRFC (min) + 10ns) tXSmax.: - Exit Self Refresh to commands requiring a locked DLL tXSDLL tXSDLLmin.: tDLLK(min) tXSDLLmax.: - nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR tCKESRmin.: tCKE(min) + 1 tCK tCKESRmax.: - Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE) tCKSRE tCKSREmin.: max(5 tCK, 10 ns) tCKSREmax.: - Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit tCKSRX tCKSRXmin.: max(5 tCK, 10 ns) tCKSRXmax.: - |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
