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NT5CB128M8GP-EKB Datasheet(PDF) 143 Page - Nanya Technology Corporation. |
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NT5CB128M8GP-EKB Datasheet(HTML) 143 Page - Nanya Technology Corporation. |
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143 / 160 page  Version 2.2 143 Nanya Technology Cooperation © 04/2019 All Rights Reserved. NTC Proprietary Level: Property DDR3(L) 1Gb SDRAM NT5CB(C)128M8GN / NT5CB(C)64M16GP Parameter Symbol DDR3(L)-1600 DDR3(L)-1866 DDR3-2133 Unit Min. Max. Min. Max. Min. Max. Data Strobe Timing DQS and low-impedance time (Referenced from RL – 1) tLZ(DQS) -450 225 -390 195 -360 180 ps DQS and high-impedance time (Referenced from RL + BL/2) tHZ(DQS) - 225 - 195 - 180 ps DQS, differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 tCK(avg) DQS, differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 tCK(avg) DQS, rising edge to CK, rising edge tDQSS -0.27 0.27 -0.27 0.27 -0.27 0.27 tCK(avg) DQS, falling edge setup time to CK, rising edge tDSS 0.18 - 0.18 - 0.18 - tCK(avg) DQS, falling edge hold time from CK, rising edge tDSH 0.18 - 0.18 - 0.18 - tCK(avg) Command and Address Timing DLL locking time tDLLK 512 - 512 - 512 - nCK Internal READ Command to PRECHARGE Command delay tRTP tRTPmin.: max(4tCK, 7.5ns) tRTPmax.: - Delay from start of internal write transaction to internal read command tWTR tWTRmin.: max(4tCK, 7.5ns) tWTRmax.: - WRITE recovery time tWR 15 - 15 - 15 - ns Mode Register Set command cycle time tMRD 4 - 4 - 4 - nCK Mode Register Set command update delay tMOD tMODmin.: max(12tCK, 15ns) tMODmax.: ACT to internal read or write delay time tRCD Refer to “FundamentalAC Specifications” PRE command period tRP ACT to ACT or REF command period tRC ACTIVE to PRECHARGE command period tRAS A to A command delay tCCD 4 - 4 - 4 - nCK Auto precharge write recovery + precharge time tDAL(MIN) WR + roundup(tRP / tCK(avg)) nCK Multi-Purpose Register Recovery Time tMPRR 1 - 1 - 1 - nCK ACTIVE to ACTIVE command period (1KB page size) tRRD max(4tCK ,6ns) - max(4tCK ,5ns) - max(4tCK ,5ns) - ACTIVE to ACTIVE command period (2KB page size) tRRD max(4tCK ,7.5ns) - max(4tCK ,6ns) - max(4tCK ,6ns) - Four activate window (1KB page size) tFAW 30 - 27 - 25 - ns Four activate window (2KB page size) tFAW 40 - 35 - 35 - ns Command and Address setup time to CK, referenced to Vih(ac) / Vil(ac) levels tIS(BASE) DDR3-1600 (AC175) DDR3-1866/ 2133(AC150) 45 - - - - - ps tIS(BASE) DDR3-1600 (AC150) DDR3-1866/ 2133(AC125) 170 - 150 - 135 - ps tIS(BASE) DDR3L (AC160) 60 - - - - ps tIS(BASE) DDR3L (AC135) 185 - 65 - - - ps tIS(BASE) DDR3L (AC125) - - 150 - - - ps Command and Address hold time from CK, referenced to Vih(dc) / Vil(dc) levels tIH(BASE) DDR3 DC100 120 - 100 - 95 - ps tIH(BASE) DDR3L DC90 130 - 110 - - - ps Control and Address Input pulse width for each input tIPW 560 - 535 - 470 - ps |
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