NT5CB128M8GP-EKB datasheet(147/160 Pages) NANYA

147 / 160 page

Version 2.2

147

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

23. One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error within 64

nCK

for all speed bins assuming the maximum sensitivities specified in the “Output Driver Voltage and Temperature

Sensitivity” and “ODT Voltage and Temperature Sensitivity” tables. The appropriate interval between ZQCS commands can be

determined from these tables and other application-specific parameters.

One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate)

drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula:

ZQCorrection / [(TSens x Tdriftrate) + (VSens x Vdriftrate)] where TSens = max(dRTTdT, dRONdTM) and VSens =

max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.

For example, if TSens = 1.5%/oC, VSens = 0.15%/mV, Tdriftrate = 1 oC/sec and Vdriftrate = 15mV/sec, then the interval

between ZQCS commands is calculated as 0.5 / [(1.5x1)+(0.15x15)] = 0.133 ~ 128ms

24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.

25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.

26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.

27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of derating to

accommodate for the lower alternate threshold of 150mV and another 25ps to account for the earlier reference point [(175mV

–

150mV) / 1V/ns]

NT5CB128M8GP-EKB Datasheet(PDF) 147 Page - Nanya Technology Corporation.