NT5CB128M8GP-EKB datasheet(146/160 Pages) NANYA

146 / 160 page

Version 2.2

146

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

Timing Parameter Notes

Actual value dependent upon measurement level definitions: See “Method for calculating tWPRE transitions and endpoints”

and “Method for calculating tWPST transitions and endpoints”.

2. Commands requiring a locked DLL are: READ ( and RAP) are synchronous ODT commands.

3. The max values are system dependent.

4. WR as programmed in mode register.

5. Value must be rounded-up to next higher integer value.

6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFi.

7. For definition of RTT-on time tAON See “Timing Parameters”.

8. For definition of RTT-off time tAOF See “Timing Parameters”.

9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR/tCK to the next integer.

10. WR in clock cycles are programmed in MR0.

11. The maximum read postamble is bounded by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side.

12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this

parameter needs to be derated by TBD.

13. Value is only valid for RON34.

14. Single ended signal parameter.

15. tREFi depends on TOPER.

16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK,  differential slew rate. Note for

DQ and DM signals, VREF(DC)=VrefDQ(DC). For input only pins except RESET, Vref(DC)=VrefCA(DC).

17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS,  differential slew rate. Note for

DQ and DM signals, VREF(DC)=VrefDQ(DC). For input only pins except RESET, Vref(DC)=VrefCA(DC).

18. Start of internal write transaction is defined as follows:

For BL8 (fixed by MRS and on-the-fly): Rising clock edge 4 clock cycles after WL.

For BC4 (on-the-fly): Rising clock edge 4 clock cycles after WL.

For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.

19. The maximum read preamble is bound by tLZ (DQS)min on the left side and tDQSCK(max) on the right side.

20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in

progress, but power-down IDD spec will not be applied until finishing those operations.

21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases

where additional time such as tXPDLL(min) is also required.

22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

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