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NT5CC128M8GP-EKB Datasheet(PDF) 116 Page - Nanya Technology Corporation. |
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NT5CC128M8GP-EKB Datasheet(HTML) 116 Page - Nanya Technology Corporation. |
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116 / 160 page  Version 2.2 116 Nanya Technology Cooperation © 04/2019 All Rights Reserved. NTC Proprietary Level: Property DDR3(L) 1Gb SDRAM NT5CB(C)128M8GN / NT5CB(C)64M16GP NOTE 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. NOTE 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS. NOTE 3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 x VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 x VDDQ and 0.8 x VDDQ. NOTE 4. Not a specification requirement, but a design guide line. NOTE 5. Measurement definition for RTT: Apply VIH(ac) to pin under test and measure current I(VIH(ac)), then apply VIL(ac) to pin under test and measure current I(VIL(ac)) respectively. NOTE 6. Measurement definition for VM and DVM: Measure voltage (VM) at test pin (midpoint) with no load: RTT = I(VIH(ac)) – I(VIL(ac)) VIH(ac) – VIL(ac) △ VM = ( – 1) x 100 VDDQ 2 x VM |
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