LMX2336UTM datasheet(29/48 Pages) NSC

29 / 48 page

Test Setups (Continued)

LMX2335U and LMX2336U f

IN Sensitivity Test Setup

10136740

The block diagram above illustrates the setup required to

measure the LMX2336U device’s RF1 input sensitivity level.

The

same

setup

used

for

the

LMX2336TMEB/

LMX2336SLEEB Evaluation Boards. The RF2 input sensitiv-

ity test setup is similar to the RF1 sensitivity test setup. The

purpose of this test is to measure the acceptable signal level

to the f

IN RF1 input of the PLL chip. Outside the acceptable

signal range, the feedback divider begins to divide incor-

rectly and miscount the frequency.

The setup uses an open loop configuration. A power supply

is connected to V

cc and the bias voltage is swept from 2.7V

to 5.5V. The RF2 PLL is powered down (PWDN RF2 Bit = 1).

By means of a signal generator, an RF signal is applied to

the f

IN RF1 pin. The 3 dB pad provides a 50

Ω match

between the PLL and the signal generator. The OSC

in pin is

tied to V

cc. The N value is typically set to 10000 in Code

Loader, i.e. RF1 N_CNTRB Word = 156 and RF1 N_CNTRA

Word = 16 for PRE RF1 Bit = 0. The feedback divider output

is routed to the F

oLD pin by selecting the RF1 PLL N Divider

Output word (F

oLD Word = 6 or 14) in Code Loader. A

Universal Counter is connected to the F

oLD pin and tied to

the 10 MHz reference output of the signal generator. The

output of the feedback divider is thus monitored and should

be equal to f

IN RF1/N.

The f

IN RF1 input frequency and power level are then swept

with the signal generator. The measurements are repeated

at different temperatures, namely T

A = -40˚C, +25˚C, and

+85˚C. Sensitivity is reached when the frequency error of the

divided RF input is greater than or equal to 1 Hz. The power

attenuation from the cable and the 3 dB pad must be ac-

counted for. The feedback divider will actually miscount if too

much or too little power is applied to the f

IN RF1 input.

Therefore, the allowed input power level will be bounded by

the upper and lower sensitivity limits. In a typical application,

if the power level to the f

IN RF1 input approaches the sen-

sitivity limits, this can introduce spurs and degradation in

phase noise. When the power level gets even closer to these

limits, or exceeds it, then the RF1 PLL loses lock.

The LMX2335U f

IN sensitivity test setup is very much similar

to the above test setup.

LMX2336UTM Datasheet(PDF) 29 Page - National Semiconductor (TI)

LMX2336UTM Datasheet(HTML) 29 Page - National Semiconductor (TI)

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