Rev.1.40

Sep 30, 2004

page 7 of 26

REJ03B0034-0140Z

R8C/11 Group

2. Central Processing Unit (CPU)

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB

comprise a register bank. There are two register banks.

2.1 Data Registers (R0, R1, R2 and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to

R3 are the same as R0.

The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.

R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-

bit data register (R2R0). R3R1 is the same as R2R0.

Data registers (Note 1)

Address registers (Note 1)

Frame base registers (Note 1)

Program counter

Interrupt table register

User stack pointer

Interrupt stack pointer

Static base register

Flag register

Note 1: These registers comprise a register bank. There are two register banks.

R0H(R0's high bits)

b15

b8 b7

b0

R3

INTBH

USP

ISP

SB

C

D

Z

S

B

O

I

U

IPL

R0L(R0's low bits)

R1H(R1's high bits)R1L(R1's low bits)

R2

b31

R3

R2

A1

A0

FB

b19

INTBL

b15

b0

PC

b19

b0

b15

b0

FLG

b15

b0

b15

b0

b7

b8

Reserved area

Carry flag

Debug flag

Zero flag

Sign flag

Register bank select flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

The upper 4 bits of INTB are INTBH and

the lower 16 bits of INTB are INTBL.

Figure 2.1. Central Processing Unit Register