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TAS5504 Datasheet(PDF) 45 Page - Texas Instruments |
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TAS5504 Datasheet(HTML) 45 Page - Texas Instruments |
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45 / 96 page ![]() TAS5504 Controls and Status 38 SLES123 − October 2004 TAS5504 SE: Single-ended configuration 2.3.2 Headphone Configuration Registers The headphone configuration controls are identical to the speaker configuration controls. The headphone configuration control settings are used in place of the speaker configuration control settings for channels 1 and 2 when the headphones are selected. In reality however, there is only one used configuration setting for headphones and that is the default setting. 2.3.3 Audio System Configurations The TAS5504 can be configured to comply with various audio systems. The audio system configuration is set in the General Control Register (0xE0). Bits D31 – D4 must be zero and D0 is don’t care. D3 Determines if SUB is to be controlled by PSVC D2 Enable/Disable power supply volume control D3−D1 must be configured as the following according to the audio system in the application: Table 2−7. Audio System Configuration (General Control Register 0xE0) AUDIO SYSTEM D31−D4 D3 D2 D1 D0 DEFAULT 0 0 0 0 X 3.1 channels NOT using PSVC 0 0 0 1 X 4 channels using PSVC 0 0 1 1 X 3.1 channels using PSVC 0 1 1 1 X 2.3.4 Recovery from Clock Error The TAS5504 can be set to either perform a volume ramp up during the recovery sequence of a clock error or to simply come up in the last state (or desired state if a volume or tone update was in progress). This feature is enabled via I2C system control register 0x03. 2.3.5 Power Supply Volume Control Enable The power supply volume control (PSVC) can be enabled and disabled via I2C register 0xE0. The subwoofer PWM output can configured to be controlled by the PSVC or digitally attenuated when PSVC is enabled (for powered subwoofer configurations). Note that PSVC cannot be simultaneously enabled along with unmute outputs after clock error feature. 2.3.6 Volume and Mute Update Rate The TAS5504 has fixed soft volume and mute ramp durations. The ramps are linear. The soft volume and mute ramp rates are adjustable by programming the I2C register 0xD0 for the appropriate number of steps to be 512, 1024, or 2048. The update is performed at a fixed rate regardless of the sample rate. • In normal speed, the update rate is 1 step every 4 / Fs seconds. • In double speed, the update is 1 step every 8 / Fs seconds. • In quad speed, the update is 1 step every 16 / Fs seconds. Because of processor loading, the update rate can increase for some increments by +1/Fs to +3/Fs. However, the variance of the total time to go from +18 dB to mute is less than 25%. |
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