TAS5504 datasheet(46/96 Pages) TI

46 / 96 page

TAS5504 Controls and Status

SLES123 − October 2004

TAS5504

Table 2−8. Volume Ramp Rates in ms

NUMBER OF STEPS

SAMPLE RATE (kHz)

NUMBER OF STEPS

44.1, 88.2, 176.4

32, 48, 96, 192

512

46.44 ms

42.67 ms

1024

92.88 ms

85.33 ms

2048

185.76 ms

170.67 ms

2.3.7 Modulation Index Limit

PWM modulation is a linear function of the audio signal. When the audio signal is 0, the PWM modulation is

50%. When the audio signal increases towards full scale, the PWM modulation increases towards 100%. For

negative signals, the PWM modulations fall below 50% towards 0%.

However, there is a limit to the maximum modulation possible. During the off-time period, the power stage

connected to the TAS5504 output needs to get ready for he next on-time period. The maximum possible

modulation is then set by the power stage requirements. A modulation index of 97.7% is the default setting

of the TAS5504. Default settings can be changed in the Modulation Index Register (0x16).

Note that no change should be made to this register when using Texas Instruments power stages.

2.3.8 Inter-channel Delay

An 8-bit value can be programmed to each of the four PWM inter-channel delay registers to add a delay per

channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK.

The default values are shown in Table 2−9.

Table 2−9. Inter-Channel Delay Default Values

I2C SUB-ADDRESS

CHANNEL

INTER-CHANNEL DELAY DEFAULT (DCLK PERIODS)

0x1B

−24

0x1C

0x21

−8

0x22

+24

This delay is generated in the PWM and can be changed at any time through the serial control interface I2C

registers 0x1B – 0x22. The absolute offset for channel 1 is set in I2C sub-address 0x23.

NOTE:If used correctly, setting the PWM channel delay can optimize the performance of a

pure path digital amplifier system. The setting is based upon the type of backend power device

that is used and the layout. These values are set during initialization using the I2C serial

interface. Unless otherwise noted, use the default values given in Table 2−9.

2.4

Master Clock and Serial Data Rate Controls

The TAS5504 function only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK (left/right

clock) signals that controls the flow of data on the four serial data interfaces. The 13.5-MHz external crystal

allows the TAS5504 to automatically detect MCLK and the data rate.

The MCLK frequency can be 64 x Fs, 128 x Fs, 196 x Fs, 256 x Fs, 384 x Fs, 512 x Fs, or 768 x Fs.

The TAS5504 operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK.

However, there is no constraint as to the phase relationship of these signals. The TAS5504 accepts a 64 x

Fs SCLK rate and a 1 x Fs LRCLK.

If the phase of SCLK or LRCLK drifts more than ±10 MCLK cycles since the last RESET, the TAS5504 performs

a clock error and resynchronize the clock timing.

The clock and serial data interface have several control parameters:

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