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MCP2517FD Datasheet(PDF) 54 Page - Microchip Technology |
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MCP2517FD Datasheet(HTML) 54 Page - Microchip Technology |
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54 / 98 page ![]() MCP2517FD DS20005688B-page 54 2017-2018 Microchip Technology Inc. bit 0 TFNRFNIE : Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit TXEN = 1 (FIFO configured as a Transmit FIFO) Transmit FIFO Not Full Interrupt Enable 1 = Interrupt enabled for FIFO not full 0 = Interrupt disabled for FIFO not full TXEN = 0 (FIFO configured as a Receive FIFO) Receive FIFO Not Empty Interrupt Enable 1 = Interrupt enabled for FIFO not empty 0 = Interrupt disabled for FIFO not empty REGISTER 3-28: CiFIFOCONm – FIFO CONTROL REGISTER m, (m = 1 TO 31) (CONTINUED) Note 1: These bits can only be modified in Configuration mode. 2: This bit is updated when a message completes (or aborts) or when the FIFO is reset. 3: FRESET is set while in Configuration mode and is automatically cleared in Normal mode. |
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