MCP2517FD datasheet(67/98 Pages) MICROCHIP

67 / 98 page

 2017-2018 Microchip Technology Inc.

DS20005688B-page 67

MCP2517FD

4.0

SPI INTERFACE

The MCP2517FD is designed to interface directly with

an Serial Peripheral Interface (SPI) port available on

most microcontrollers. The SPI in the microcontroller

must be configured in mode 0,0 or 1,1 in 8-bit operating

mode.

SFR and Message Memory (RAM) are accessed using

SPI instructions. Figure 4-1 illustrates the generic for-

mat of the SPI instructions (SPI mode 0,0). Each

instruction starts with driving nCS low (falling edge on

nCS). The 4-bit command and the 12-bit address are

shifted into SDI on the rising edge of SCK. During a

write instruction, data bits are shifted into SDI on the

rising edge of SCK. During a read instruction, data bits

are shifted out of SDO on the falling edge of SCK. One

or more data bytes are transfered with one instruction.

Data bits are updated on the falling edge of SCK and

must be valid on the rising edge of SCK. Each instruc-

tion ends with driving nCS high (rising edge on nCS).

Refer to Figure 7-1 for detailed input and output timing

for both mode 0,0 and mode 1,1.

Table 4-1 lists the SPI instructions and their format.

FIGURE 4-1:

SPI INSTRUCTION FORMAT

TABLE 4-1:

SPI INSTRUCTIONS

Note 1:

The frequency of SCK has to be less than

or equal to half the frequency of SYSCLK.

This ensures that the synchronization

between SCK and SYSCLK works

correctly.

In order to minimize the Sleep current, the

SDO pin of the MCP2517FD must not be

left floating while the device is in Sleep

mode. This can be achieved by enabling

a pull-up or pull-down resistor inside the

MCU on the pin that is connected to the

SDO pin of the MCP2517FD, while the

MCP2517FD is in Sleep mode.

123

567

910

nCS

SCK

SDI

SDO

C<3>

C<2>

C<1>

C<0>

A<11> A<10>

A<9>

A<8>

A<7>

A<6>

A<5>

A<4>

A<3>

A<2>

A<1>

A<0>

D<7>

D<6>

D<5>

D<4>

D<3>

D<2>

D<1>

D<0>

D<7>

D<6>

D<5>

D<4>

D<3>

D<2>

D<1>

D<0>

Sample

Update

Sample

Update

Name

Format

Description

RESET

C = 0b0000; A = 0x000 Resets internal registers to default state; selects Configuration mode.

READ

C = 0b0011; A; D = SDO Read SFR/RAM from address A.

WRITE

C = 0b0010; A; D = SDI Write SFR/RAM to address A.

READ_CRC

C = 0b1011; A; N;

D = SDO; CRC = SDO

Read SFR/RAM from address A. N data bytes. Two bytes CRC.

CRC is calculated on C, A, N and D.

WRITE_CRC

C = 0b1010; A; N;

D = SDI; CRC = SDI

Write SFR/RAM to address A. N data bytes. Two bytes CRC.

CRC is calculated on C, A, N and D.

WRITE_SAFE C = 0b1100; A;

D = SDI; CRC = SDI

Write SFR/RAM to address A. Check CRC before write. CRC is calculated

on C, A and D.

Legend:

C = Command (4 bit), A = Address (12 bit), D = Data (1 to n bytes), N = Number of Bytes (1 byte), CRC (2

bytes)

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