ADMV4530 datasheet(9/59 Pages) AD

9 / 59 page

Data Sheet

ADMV4530

Rev. A | Page 9 of 59

Pin No.

Mnemonic

Description

Power-Down, 3.3 V Logic. Active high.

CPOUT

Charge Pump Output. Connect this pin to VTUNE (Pin 20) through the loop filter.

SPI Chip Select. 3.3 V logic. Active low.

SDI

SPI Data Input. 3.3 V logic.

SCLK

SPI Clock. 3.3 V logic.

SDO

SPI Data Output. 3.3 V logic.

CREG

External Capacitor for the Low Dropout (LDO) Regulator Output. Place a 0.1 µF decoupling

capacitor close to this pin.

VCC_LDO

Supply Voltage for the Internal LDO Regulator, 3.3 V. Place a 1 µF decoupling capacitor close

to this pin.

VCC_CP

Supply Voltage for the Charge Pump, 3.3 V. Place a 1 µF decoupling capacitor close to this pin.

RST

Reset. 3.3 V logic. Active low.

REF_IN

PLL Reference Input. Apply an external reference signal to this pin with a 0.01 µF, dc blocking

capacitor. Refer to Figure 91 for the external reference input configuration.

VCC_1P8V

Supply Voltage for the SPI Block, 1.8 V. Place a 1 µF decoupling capacitor close to this pin.

37, 39

GND

Ground. Connect these pins to RF and dc ground.

RFOUT

RF Output. This pin has a 50 Ω output impedance.

EPAD

Exposed Pad. Connect the exposed pad to RF and dc ground.

ADMV4530 Datasheet(PDF) 9 Page - Analog Devices