MWCT1004AFVLLPR datasheet(18/65 Pages) NXP

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5.2 General AC specifications

These general purpose specifications apply to all signals configured for GPIO, UART,

and timers.

Table 8. General switching specifications

Symbol

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5

—

Bus clock

cycles

1, 2

GPIO pin interrupt pulse width (digital glitch filter

disabled, passive filter disabled) — Asynchronous path

—

WFRST

RESET input filtered pulse

—

WNFRST

RESET input not filtered pulse

Maximum of

(100 ns, bus

clock period)

—

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In Stop and VLPS modes, the synchronizer is bypassed so shorter pulses can be recognized in

that case.

2. The greater of synchronous and asynchronous timing must be met.

3. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized.

4. Maximum length of RESET pulse which will be filtered by internal filter.

5. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter. This number depends on bus clock

period also. For example, in VLPR mode bus clock is 4 MHz, which make clock period of 250 ns. In this case, minimum

pulse width which will cause reset is 250 ns. For faster bus clock frequencies which have clock period less than 100 ns,

the minimum pulse width not filtered will be 100 ns.

5.3 DC electrical specifications at 3.3 V Range

NOTE

For details on the pad types defined in Table 9 and Table 10,

see Reference Manual section IO Signal Table and IO Signal

Description Input Multiplexing sheet(s) attached with

Reference Manual.

Table 9. DC electrical specifications at 3.3 V Range

Symbol

Parameter

Value

Unit

Notes

Min.

Typ.

Max.

VDD

I/O Supply Voltage

2.7

3.3

Vih

Input Buffer High Voltage

0.7 × VDD

—

VDD + 0.3

Vil

Input Buffer Low Voltage

VSS − 0.3

—

0.3 × VDD

Vhys

Input Buffer Hysteresis

0.06 × VDD

—

IohGPIO

I/O current source capability measured when

pad Voh = (VDD − 0.8 V)

3.5

—

Table continues on the next page...

I/O parameters

MWCT101XS Data Sheet, Rev. 3, 12/2019

NXP Semiconductors

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