MWCT1004AFVLLPR datasheet(25/65 Pages) NXP

25 / 65 page

Table 15. External System Oscillator electrical specifications

(continued)

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

High-gain mode (HGO=1)

—

MΩ

Series resistor

Low-gain mode (HGO=0)

—

kΩ

High-gain mode (HGO=1)

—

kΩ

Vpp

Peak-to-peak amplitude of oscillation (oscillator mode)

Low-gain mode (HGO=0)

—

1.0

—

High-gain mode (HGO=1)

—

3.3

—

1. Crystal oscillator circuit provides stable oscillations when gmXOSC > 5 * gm_crit. The gm_crit is defined as:

gm_crit = 4 * ESR * (2πF)2 * (C0 + CL)2

where:

• gmXOSC is the transconductance of the internal oscillator circuit

• ESR is the equivalent series resistance of the external crystal

• F is the external crystal oscillation frequency

• C0 is the shunt capacitance of the external crystal

• CL is the external crystal total load capacitance. CL = Cs+ [C1*C2/(C1+C2)]

• Cs is stray or parasitic capacitance on the pin due to any PCB traces

• C1, C2 external load capacitances on EXTAL and XTAL pins

See manufacture datasheet for external crystal component values

• When low-gain is selected, internal RF will be selected and external RF should not be attached.

• When high-gain is selected, external RF (1 M Ohm) needs to be connected for proper operation of the crystal. For

external resistor, up to 5% tolerance is allowed.

3. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any

other devices.

6.2.2 External System Oscillator frequency specifications

Table 16. External System Oscillator frequency specifications

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

fosc_hi

Oscillator crystal or resonator frequency

—

MHz

fec_extal

Input clock frequency (external clock mode)

—

MHz

tdc_extal

Input clock duty cycle (external clock mode)

tcst

Crystal Start-up Time

8 MHz low-gain mode (HGO=0)

—

1.5

—

8 MHz high-gain mode (HGO=1)

—

2.5

—

40 MHz low-gain mode (HGO=0)

—

40 MHz high-gain mode (HGO=1)

—

1. Frequencies below 40 MHz can be used for degraded duty cycle up to 40-60%

2. Proper PC board layout procedures must be followed to achieve specifications.

Clock interface modules

MWCT101XS Data Sheet, Rev. 3, 12/2019

NXP Semiconductors

MWCT1004AFVLLPR Datasheet(PDF) 25 Page - NXP Semiconductors

MWCT1004AFVLLPR Datasheet(HTML) 25 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

Datasheet Download

Link URL