MWCT1004AFVLLPR datasheet(49/65 Pages) NXP

Part #	MWCT1004AFVLLPR

Description	Memory and memory interfaces

PDF	65 Pages

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Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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49 / 65 page

MSB IN

BIT 6 . . . 1

SLAVE MSB

SLAVE LSB OUT

See

note 1

See

note1

(INPUT)

(CPOL=0)

SPSCK

(CPOL=1)

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

LSB IN

BIT 6 . . . 1

Notes:

1. Undefined

Figure 19. LPSPI slave mode timing (CPHA = 0)

MSB IN

BIT 6 . . . 1

MSB OUT

SLAVE LSB OUT

SLAVE

See

note 1

(INPUT)

(CPOL=0)

SPSCK

(CPOL=1)

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

LSB IN

BIT 6 . . . 1

Notes:

1. Undefined

Figure 20. LPSPI slave mode timing (CPHA = 1)

6.5.3 LPI2C electrical specifications

See General AC specifications for LPI2C specifications.

For supported baud rate see section 'Chip-specific LPI2C information' of the Reference

Manual.

Communication modules

MWCT101XS Data Sheet, Rev. 3, 12/2019

NXP Semiconductors

MWCT1004AFVLLPR Datasheet(PDF) 49 Page - NXP Semiconductors

MWCT1004AFVLLPR Datasheet(HTML) 49 Page - NXP Semiconductors

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