DS160PR412RUAR datasheet(4/37 Pages) TI

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Table 5-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

EQ0 /ADDR

I, 4-level

In Pin Mode:

The EQ0 and EQ1 pins sets receiver linear equalization CTLE (AC gain) for all

channels according to Table 7-1. These pins are sampled at device power-up only.

In SMBus/I2C Mode:

The ADDR pin in conjunction with MODE pin sets SMBus / I2C slave address

according to Table 7-4. The pin is sampled at device power-up only.

EQ1

I, 4-level

GAIN /SDA

I, 4-level / IO

In Pin Mode:

DC gain (broadbad gain including high frequency) from the input to the output of

the device for all channels. Note the device also provides AC (high frequency)

gain in the form of equalization controlled by EQ pins or SMBus/I2C registers.

In SMBus/I2C Mode:

3.3 V SMBus/I2C data. External pullup resistor such as 4.7 kΩ required for

operation.

GND

EP, 6, 9, 16,

21, 30, 39

Ground reference for the device.

EP: the Exposed Pad at the bottom of the QFN package. It is used as the GND

return for the device. The EP should be connected to ground plane(s) through low

resistance path. A via array provides a low impedance path to GND. The EP also

improves thermal dissipation.

RSVD

TI internal test pin. Keep no connect.

I, 3.3-V LVCMOS 2-level logic controlling the operating state of the redriver. Active in both Pin Mode

and SMBus/I2C Mode. The pin is used part of PCIe RX_DET state machine as

outlined in Table 7-2.

High: Power down for all channels

Low: Power up, normal operation for all channels

RX_DET /SCL

I, 4-level / IO

In Pin Mode:

Sets receiver detect state machine options according to Table 7-2. The pin is

sampled at device power-up only.

In SMBus/I2C Mode:

3.3 V SMBus/I2C clock. External pullup resistor such as 4.7 kΩ required for

operation.

RX0N

Inverting differential RX inputs. Channel 0.

RX0P

Noninverting differential RX inputs. Channel 0.

RX1N

Inverting differential RX inputs. Channel 1.

RX1P

Noninverting differential RX inputs. Channel 0.

RX2N

Inverting differential RX inputs. Channel 2.

RX2P

Noninverting differential RX inputs. Channel 2.

RX3N

Inverting differential RX inputs. Channel 3.

RX3P

Noninverting differential RX inputs. Channel 3.

SEL

I, 3.3 V LVCMOS Selects the mux path. Active in both Pin Mode and SMBus/I2C Mode. Note the

SEL pin must be exercised in system implementations for mux selection between

Port A vs Port B. The pin is used part of PCIe RX_DET state machine as outlined

in Table 7-2.

L: Port A selected.

H: Port B selected.

TXA0N

Inverting differential TX output – Port A, Channel 0.

TXA0P

Non-inverting differential TX output – Port A, Channel 0.

TXA1N

Inverting differential TX output – Port A, Channel 1.

TXA1P

Non-inverting differential TX output – Port A, Channel 1.

TXA2N

Inverting differential TX output – Port A, Channel 2.

TXA2P

Non-inverting differential TX output – Port A, Channel 2.

TXA3N

Inverting differential TX output – Port A, Channel 3.

TXA3P

Non-inverting differential TX output – Port A, Channel 3.

TXB0N

Inverting differential TX output – Port B, Channel 0.

DS160PR412

SNLS685 – DECEMBER 2020

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