Table 7-2. Receiver Detect State Machine Settings (continued)

PD

RX_DET

RX Common-mode Impedance

COMMENTS

L

L3 (Float)

Pre Detect: Hi-Z

Post Detect: 50 Ω.

TX polls every ≈150 µs until valid termination is detected. RX CM

impedance held at Hi-Z until detection Reset by asserting PD high

for 200 µs then low.

H

X

Hi-Z

Reset Channels 0-3 signal path and set their RX impedance to Hi-

Z

L

X

Pre Detect: Hi-Z

Post Detect: 50 Ω.

Reset Channels 4-7 signal path and set their RX impedance to Hi-

Z.

H

X

Hi-Z

7.4 Device Functional Modes

7.4.1 Active PCIe Mode

The device is in normal operation with PCIe state machine enabled by RX_DET = L3 (float). This mode is

recommended for PCIe use cases. In this mode PD pin is driven low in a system (for example by PCIe connector

"PRSNT" signal). In this mode, the device redrives and equalizes PCIe RX or TX signals to provide better signal

integrity.

7.4.2 Active Buffer Mode

The device is in normal operation with PCIe state machine disabled by RX_DET = L0. This mode is

recommended for non-PCIe use cases. In this mode the device is working as a buffer to provide linear

equalization to improve signal integrity.

7.4.3 Standby Mode

The device is in standby mode invoked by PD = H. In this mode, the device is in standby mode conserving

power.

7.5 Programming

7.5.1 Control and Configuration Interface

7.5.1.1 Pin Mode

The DS160PR412 can be fully configured through pin-strap pins. In this mode the device uses 2-level and 4-

level pins for device control and signal integrity optimum settings.

7.5.1.1.1 Four-Level Control Inputs

The DS160PR412 has five (EQ0, EQ1, GAIN, MODE, and RX_DET) 4-level inputs pins that are used to control

the configuration of the device. These 4-level inputs use a resistor divider to help set the 4 valid levels and

provide a wider range of control settings. External resistors must be of 10% tolerance or better. The EQ0, EQ1,

GAIN, and RX_DET pins are sampled at power-up only. The MODE pin can be exercised at device power up or

in normal operation mode.

Table 7-3. 4-Level Control Pin Settings

LEVEL

SETTING

L0

1 kΩ to GND

L1

13 kΩ to GND

L2

59 kΩ to GND

L3

F (Float)

determined by the pin strap settings on the ADDR and MODE pins. The eight possible slave addresses (7-bit) for

DS160PR412

SNLS685 – DECEMBER 2020

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