DS160PR412RUAR datasheet(9/37 Pages) TI

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over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TPLHD/PHLD

Input-to-output latency (propagation

delay) through a data channel

For either Low-to-High or High-to-Low

transition

110

LTX-SKEW

Lane-to-Lane Output Skew

Between any two lanes within a single

transmitter.

-20

TRJ-DATA

Additive Random Jitter with data

Difference between through redriver

and baseline setup. 16Gbps PRBS15.

Minimal input/output

channels. Minimum EQ. 800 mVpp-diff

input swing.

TRJ-INTRINSIC

Intrinsic additive Random Jitter with

clock

Difference between through redriver

and baseline setup. 8 Ghz CK.

Minimal input/output

channels. Minimum EQ. 400 mVpp-diff

input swing.

JITTERTOTAL-

DATA

Additive Total Jitter with data

Difference between through redriver

and baseline setup. 16 Gbps PRBS15.

Minimal input/output

channels. Minimum EQ. 800 mVpp-diff

input swing.

JITTERTOTAL-

INTRINSIC

Intrinsic additive Total Jitter with clock

Difference between through redriver

and baseline setup. 8 Ghz CK.

Minimal input/output

channels. Minimum EQ. 800 mVpp-diff

input swing.

DCGAIN

DC flat gain input to output

Minimum EQ, GAIN = L0

-4.2

Minimum EQ, GAIN = L1

-1.8

Minimum EQ, GAIN = L2

0.25

Minimum EQ, GAIN = L3 (Float)

2.0

EQ-MAX8G

EQ boost at max setting (EQ INDEX =

15)

AC gain at 8 GHz relative to gain at

100 MHz.

DCGAINVAR

DC gain variation

GAIN = L2, minimum EQ setting. Max-

Min.

-2.3

1.7

EQGAINVAR

EQ boost variation

At 8 Ghz. GAIN1/0 = L2, maximum EQ

setting. Max-Min.

-3.3

3.7

LINDC

Output DC Linearity

GAIN = L3 (defauult). 128T pattern at

2.5 Gbps.

1000

mVpp

LINAC

Output AC Linearity

GAIN = L3 (default). 1T pattern at 16

Gbps.

750

mVpp

6.7 SMBUS/I2C Timing Charateristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Slave Mode

tSP

Pulse width of spikes which must be

suppressed by the input filter

tHD-STA

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated

0.6

µs

tLOW

LOW period of the SCL clock

1.3

µs

THIGH

HIGH period of the SCL clock

0.6

µs

tSU-STA

Set-up time for a repeated START

condition

0.6

µs

tHD-DAT

Data hold time

µs

TSU-DAT

Data setup time

0.1

µs

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DS160PR412

SNLS685 – DECEMBER 2020

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