8.2.1.1 Design Requirements

As with any high-speed design, there are many factors which influence the overall performance. The following

list indicates critical areas for consideration during design.

• Use 85 Ω impedance traces when interfacing with PCIe CEM connectors. Length matching on the P and N

traces should be done on the single-ended segments of the differential pair.

• Use a uniform trace width and trace spacing for differential pairs.

• Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.

• For Gen 3.0 and Gen 4.0, AC-coupling capacitors of 220 nF are recommended, set the maximum body size

to 0402, and add a cutout void on the GND plane below the landing pad of the capacitor to reduce parasitic

capacitance to GND.

• Back-drill connector vias and signal vias to minimize stub length.

• Use reference plane vias to ensure a low inductance path for the return current.

8.2.1.2 Detailed Design Procedure

In PCIe Gen 4.0 and Gen 3.0 applications, the specification requires Rx-Tx link training to establish and optimize

signal conditioning settings at 16 Gbps and 8 Gbps, respectively. In link training, the Rx partner requests a series

of FIR – pre-shoot and de-emphasis coefficients (10 Presets) from the Tx partner. The Rx partner includes 7-

levels (6 dB to 12 dB) of CTLE followed by a single tap DFE. The link training would pre-condition the signal,

with an equalized link between the root-complex and endpoint.

Note that there is no link training in PCIe Gen 1.0 (2.5 Gbps) or PCIe Gen 2.0 (5.0 Gbps) applications. The

DS160PR412 is placed in between the Tx and Rx. It helps extend the PCB trace reach distance by boosting the

attenuated signals with its equalization, which allows the user to recover the signal by the downstream Rx more

easily.

For operation in Gen 4.0 and Gen 3.0 links, the DS160PR412 transmit outputs are designed to pass the Tx

Preset signaling onto the Rx for the PCIe Gen 4.0 or Gen 3.0 link to train and optimize the equalization settings.

The suggested setting for the device is GAIN = L3 (default). Adjustments to the EQ setting should be performed

based on the channel loss to optimize the eye opening in the Rx partner. The Tx equalization presets or CTLE

and DFE coefficients in the Rx can also be adjusted to further improve the eye opening.

8.2.1.3 Pin-to-pin Passive versus Redriver Option

For eight lane PCIe lane muxing application a topology is illustrated where two DS160PR412 and two

DS160PR421 are used. There are system use cases where the PCIe link loss is low enough that a signal

conditioner such as linear redrivers may not be needed. In such use cases system engineers may consider

passive mux to achieve same lane muxing topology. The four channel passive mux/demux TMUXHS4412 is pin-

to-pin (p2p) compatible with the DS160PR412 and DS160PR421 . This p2p component availability provides

great flexibility for system implementation engineers where the need for redriver is not completely clear. Figure

8-2 illustrates p2p passive vs redriver option to implement PCIe lane switching.

Connector-B

CPU

Connector-A

x8

Slot

x8

x16

Slot

x8

PCIe Card

PCIe Card

TXB 8-ch

RXB 8-ch

RX 8-ch

TX 8-ch

x8

TMUXHS4412

4 Ch 1:2 demux

TMUXHS4412

4 Ch 2:1 Mux

Pin-2-pin

Passive option

Connector-B

CPU

Connector-A

x8

Slot

x8

x16

Slot

x8

PCIe Card

PCIe Card

TXB 8-ch

RXB 8-ch

RX 8-ch

TX 8-ch

x8

DS160PR412

4 Ch 1:2 redriver demux

DS160PR421

4 Ch 2:1 redriver mux

Redriver option

Figure 8-2. Pin-to-pin passive vs redriver option for PCIe lane switching

DS160PR412

SNLS685 – DECEMBER 2020

www.ti.com

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