AM6421 datasheet(147/237 Pages) TI

147 / 237 page

7.10.5.8.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode

NO.

(2)

PARAMETER

DESCRIPTION

MODE

(18)

MIN

MAX

MIN

MAX

UNIT

100 MHz

133 MHz

1 / tc(clk)

Period, output clock GPMC_CLK

(16)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

10.00

7.52

tw(clkH)

Typical pulse duration, output clock

GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-0.3+0.

475*P

(14)

-0.3+0.

475*P

(14)

tw(clkL)

Typical pulse duration, output clock

GPMC_CLK low

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-0.3+0.

475*P

(14)

-0.3+0.

475*P

(14)

tdc(clk)

Duty cycle error, output clock

GPMC_CLK

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-500.00 500.00 -500.00 500.00

tJ(clk)

Jitter standard deviation, output clock

GPMC_CLK

(17)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

33.33

tR(clk)

Rise time, output clock GPMC_CLK

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.00

tF(clk)

Fall time, output clock GPMC_CLK

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.00

tR(do)

Rise time, output data

GPMC_AD[15:0]

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.00

tF(do)

Fall time, output data

GPMC_AD[15:0]

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.00

td(clkH-csnV)

Delay time, output clock GPMC_CLK

rising edge to output chip select

GPMC_CSn[i] transition

(13)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.2+F

(5)

3.75+F -2.2+F

(5)

3.75+F

td(clkH-CSn[i]V)

Delay time, output clock GPMC_CLK

rising edge to output chip select

GPMC_CSn[i] invalid

(13)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.2+E

(4)

1.3089

027178

0544+E

-2.2+E

(4)

4.5+E

td(aV-clk)

Delay time, output address

GPMC_A[27:1] valid to output clock

GPMC_CLK first edge

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+B

(2)

4.5+B -2.3+B

(2)

4.5+B

td(clkH-aIV)

Delay time, output clock GPMC_CLK

rising edge to output address

GPMC_A[27:1] invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.30

4.50

-2.30

4.50

td(be[x]nV-clk)

Delay time, output lower byte enable

and command latch enable

GPMC_BE0n_CLE, output upper byte

enable GPMC_BE1n valid to output

clock GPMC_CLK first edge

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+B

(2)

1.9+B -2.3+B

(2)

1.9+B

td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK

rising edge to output lower byte

enable and command latch enable

GPMC_BE0n_CLE, output upper byte

enable GPMC_BE1n invalid

(10)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+D

(3)

1.9+D -2.3+D

(3)

1.9+D

td(clkL-be[x]nIV)

Delay time, GPMC_CLK falling edge

to GPMC_BE0n_CLE, GPMC_BE1n

invalid

(11)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+D

(3)

1.9+D -2.3+D

(3)

1.9+D

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