AM6421 datasheet(148/237 Pages) TI

148 / 237 page

NO.

(2)

PARAMETER

DESCRIPTION

MODE

(18)

MIN

MAX

MIN

MAX

UNIT

100 MHz

133 MHz

td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge

to GPMC_BE0n_CLE, GPMC_BE1n

invalid

(12)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+D

(3)

1.9+D -2.3+D

(3)

1.9+D

td(clkH-advn)

Delay time, output clock GPMC_CLK

rising edge to output address valid

and address latch enable

GPMC_ADVn_ALE transition

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.3+G

(6)

4.5+G -2.3+G

(6)

4.5+G

td(clkH-advnIV)

Delay time, output clock GPMC_CLK

rising edge to output address valid

and address latch enable

GPMC_ADVn_ALE invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.3+D

(3)

4.5+D -2.3+D

(3)

4.5+D

F10 td(clkH-oen)

Delay time, output clock GPMC_CLK

rising edge to output enable

GPMC_OEn_REn transition

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.3H

(7)

3.5+H -2.3+H

(7)

3.5+H

F11 td(clkH-oenIV)

Delay time, output clock GPMC_CLK

rising edge to output enable

GPMC_OEn_REn invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.3+E

(7)

3.5+E -2.3+E

(7)

3.5+E

F14 td(clkH-wen)

Delay time, output clock GPMC_CLK

rising edge to output write enable

GPMC_WEn transition

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.3+I

(8)

4.5+I

-2.3+I

(8)

4.5+I

F15 td(clkH-do)

Delay time, output clock GPMC_CLK

rising edge to output data

GPMC_AD[15:0] transition

(10)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+J

(9)

2.7+J

-2.3+J

(9)

2.7+J

F15 td(clkL-do)

Delay time, GPMC_CLK falling edge

to GPMC_AD[15:0] data bus

transition

(11)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+J

(9)

2.7+J

-2.3+J

(9)

2.7+J

F15 td(clkL-do).

Delay time, GPMC_CLK falling edge

to GPMC_AD[15:0] data bus

transition

(12)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+J

(9)

2.7+J

-2.3+J

(9)

2.7+J

F17 td(clkH-be[x]n)

Delay time, output clock GPMC_CLK

rising edge to output lower byte

enable and command latch enable

GPMC_BE0n_CLE transition

(10)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+J

(9)

1.9+J

-2.3+J

(9)

1.9+J

F17 td(clkL-be[x]n)

Delay time, GPMC_CLK falling edge

to GPMC_BE0n_CLE, GPMC_BE1n

transition

(11)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+J

(9)

1.9+J

-2.3+J

(9)

1.9+J

F17 td(clkL-be[x]n).

Delay time, GPMC_CLK falling edge

to GPMC_BE0n_CLE, GPMC_BE1n

transition

(12)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+J

(9)

1.9+J

-2.3+J

(9)

1.9+J

F18 tw(csnV)

Pulse duration, output chip select

GPMC_CSn[i] low

(13)

Read

0+A

Write

0+A

F19 tw(be[x]nV)

Pulse duration, output lower byte

enable and command latch enable

GPMC_BE0n_CLE, output upper byte

enable GPMC_BE1n low

Read

0+C

Write

0+C

F20 tw(advnV)

Pulse duration, output address valid

and address latch enable

GPMC_ADVn_ALE low

Read

0+K

Write

0+K

(1)

For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)

For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)

For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)

With n being the page burst access number.

(2)

B = ClkActivationTime × GPMC_FCLK(15)

(3)

For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)

AM6442, AM6441, AM6421

AM6412, AM6411

SPRSP56 – JANUARY 2021

www.ti.com

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Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411

AM6421 Datasheet(PDF) 148 Page - Texas Instruments

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