AM6421 datasheet(175/237 Pages) TI

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Table 7-57. MMC0 Timing Requirements – Legacy SDR Mode (continued)

see Figure 7-57

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

SSDR8

th(clkH-dV)

Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge

27.97

Figure 7-57. MMC0 – Legacy SDR – Receive Mode

Table 7-58. MMC0 Switching Characteristics – Legacy SDR Mode

see Figure 7-58

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMC0_CLK

MHz

SSDR1

tc(clk)

Cycle time, MMC0_CLK

SSDR2H

tw(clkH)

Pulse duration, MMC0_CLK high

18.7

SSDR2L

tw(clkL)

Pulse duration, MMC0_CLK low

18.7

SSDR3

td(clkL-cmdV)

Delay time, MMC0_CLK falling edge to MMC0_CMD transition

-16.1

16.1

SSDR4

td(clkL-dV)

Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition

-16.1

16.1

SSDR2L

MMC0_CLK

MMC0_CMD

MMC0_DAT[7:0]

SSDR1

SSDR2H

SSDR3

SSDR4

J7_MMC0_TIMING_02

Figure 7-58. MMC0 – Legacy SDR – Transmit Mode

7.10.5.12.1.2 High Speed SDR Mode

Table 7-59, Figure 7-59, Table 7-60, and Figure 7-60 present timing requirements and switching characteristics

for MMC0 – High Speed SDR Mode.

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