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AM6421 Datasheet(PDF) 177 Page - Texas Instruments |
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AM6421 Datasheet(HTML) 177 Page - Texas Instruments |
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177 / 237 page  Table 7-61. MMC0 Timing Requirements – High Speed DDR Mode (continued) see Figure 7-61 NO. PARAMETER DESCRIPTION MIN MAX UNIT DDR8 th(clk-dV) Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition 1.76 ns MMC0 CLK _ MMC0 CMD _ MMC0 DAT[7:0] _ DDR1 DDR2H DDR2L DDR3 DDR4 DDR7 DDR8 DDR7 DDR8 DDR7 DDR8 DDR7 J7_MMC0_TIMING_05 DDR8 Figure 7-61. MMC0 – High Speed DDR Mode – Receive Mode Table 7-62. MMC0 Switching Characteristics – High Speed DDR Mode see Figure 7-62 NO. PARAMETER DESCRIPTION MIN MAX UNIT fop(clk) Operating frequency, MMC0_CLK 50 MHz DDR1 tc(clk) Cycle time, MMC0_CLK 20 ns DDR2H tw(clkH) Pulse duration, MMC0_CLK high 9.2 ns DDR2L tw(clkL) Pulse duration, MMC0_CLK low 9.2 ns DDR5 td(clk-cmdV) Delay time, MMC0_CLK rising edge to MMC0_CMD transition 3.31 16.19 ns DDR6 td(clk-dV) Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition 2.81 6.94 ns MMC0 CLK _ MMC0 CMD _ MMC0 DAT[7:0] _ DDR1 DDR2 DDR2 DDR5 DDR5 DDR6 DDR6 DDR6 DDR6 DDR5 DDR6 DDR6 J7_MMC0_TIMING_06 DDR5 Figure 7-62. MMC0 – High Speed DDR Mode – Transmit Mode 7.10.5.12.1.4 HS200 Mode Table 7-63 and Figure 7-63 present switching characteristics for MMC0 – HS200 Mode. Table 7-63. MMC0 Switching Characteristics – HS200 Mode see Figure 7-63 NO. PARAMETER DESCRIPTION MIN MAX UNIT fop(clk) Operating frequency, MMC0_CLK 200 MHz HS2001 tc(clk) Cycle time, MMC0_CLK 5 ns HS2002H tw(clkH) Pulse duration, MMC0_CLK high 2.08 ns www.ti.com AM6442, AM6441, AM6421 AM6412, AM6411 SPRSP56 – JANUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 177 Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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