AM6421 datasheet(199/237 Pages) TI

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7.10.5.16.6.1 PRU_ICSSG MDIO Timing

Table 7-103, Table 7-104, Table 7-105, and Figure 7-100 present timing conditions, requirements, and switching

characteristics for PRU_ICSSG MDIO.

Table 7-103. PRU_ICSSG MDIO Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.9

3.6

V/ns

OUTPUT CONDITIONS

Output load capacitance

470

Table 7-104. PRU_ICSSG MDIO Timing Requirements

see Figure 7-100

NO.

PARAMETER

MIN

MAX

UNIT

MDIO1 tsu(MDIO_MDC)

Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high

MDIO2 th(MDC_MDIO)

Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high

Table 7-105. PRU_ICSSG MDIO Switching Characteristics

see Figure 7-100

NO.

PARAMETER

MIN

MAX

UNIT

MDIO3 tc(MDC)

Cycle time, MDIO[x]_MDC

400

MDIO4 tw(MDCH)

Pulse Duration, MDIO[x]_MDC high

160

MDIO5 tw(MDCL)

Pulse Duration, MDIO[x]_MDC low

160

MDIO7 td(MDC_MDIO)

Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid

-150

150

MDIO3

MDIO1

MDIO2

MDIO7

MDIO4

MDIO5

MDIO[x]_MDC

MDIO[x]_MDIO

(input)

MDIO[x]_MDIO

(output)

CPSW2G_MDIO_TIMING_01

Figure 7-100. PRU_ICSSG MDIO Timing Requirements and Switching Characteristics

7.10.5.16.6.2 PRU_ICSSG MII Timing

Note

In order to ensure the MII_G_RT I/O timing values published in the device data sheet, the

PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 1) core clock must be configured for 200 MHz,

225 MHz, or 250 MHz and the TX_CLK_DELAYn (where n = 0 or 1) bit field in the ICSSG_TXCFG0/1

Table 7-106, Table 7-107, Figure 7-101, Table 7-108, Figure 7-102, Table 7-109, Figure 7-103, Table 7-110, and

Figure 7-104 present timing conditions, requirements, and switching characteristics for PRU_ICSSG MII.

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