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AM6421 Datasheet(PDF) 201 Page - Texas Instruments |
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AM6421 Datasheet(HTML) 201 Page - Texas Instruments |
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201 / 237 page  MII_RX_CLK PMIR4 PMIR5 MII_RXD[3:0], MII_RX_DV, MII_RX_ER Figure 7-102. PRU_ICSSG MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER Timing Table 7-109. PRU_ICSSG MII Timing Requirements – MII[x]_TX_CLK see Figure 7-103 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIT1 tc(TX_CLK) Cycle time, MII[x]_TX_CLK 10 Mbps 399.96 400.04 ns 100 Mbps 39.996 40.004 ns PMIT2 tw(TX_CLKH) Pulse Duration, MII[x]_TX_CLK High 10 Mbps 140 260 ns 100 Mbps 14 26 ns PMIT3 tw(TX_CLKL) Pulse Duration, MII[x]_TX_CLK Low 10 Mbps 140 260 ns 100 Mbps 14 26 ns MII_TX_CLK PMIT2 PMIT3 PMIT1 Figure 7-103. PRU_ICSSG MII[x]_TX_CLK Timing Table 7-110. PRU_ICSSG MII Switching Characteristics – MII[x]_TXD[3:0] and MII[x]_TX_EN see Figure 7-104 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIT4 td(TX_CLK-TXD) Delay time, MII[x]_TX_CLK High to MII[x]_TXD[3:0] valid 10 Mbps 0 25 ns td(TX_CLK-TX_EN) Delay time, MII[x]_TX_CLK to MII[x]_TX_EN valid 0 25 ns td(TX_CLK-TXD) Delay time, MII[x]_TX_CLK High to MII[x]_TXD[3:0] valid 100 Mbps 0 25 ns td(TX_CLK-TX_EN) Delay time, MII[x]_TX_CLK to MII[x]_TX_EN valid 0 25 ns PMIT4 MII_TX_CLK MII_TXD[3:0], MII_TX_EN Figure 7-104. PRU_ICSSG MII[x]_TXD[3:0], MII[x]_TX_EN Timing 7.10.5.16.6.3 PRU_ICSSG RGMII Timing Table 7-111, Table 7-112, Table 7-113, Figure 7-105, Table 7-114, Table 7-115, and Figure 7-106 present timing conditions, requirements, and switching characteristics for PRU_ICSSG RGMII. Table 7-111. PRU_ICSSG RGMII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 2.65 5 V/ns OUTPUT CONDITIONS www.ti.com AM6442, AM6441, AM6421 AM6412, AM6411 SPRSP56 – JANUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 201 Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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