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AM6421 Datasheet(PDF) 196 Page - Texas Instruments |
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AM6421 Datasheet(HTML) 196 Page - Texas Instruments |
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196 / 237 page  Table 7-94. PRU_ICSSG IEP Timing Requirements – Input Validated with SYNC (continued) see Figure 7-94 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRIEP2 tw(EDC_SYNC_OUTxH) Pulse duration, EDC_SYNC_OUTx high -2+20*P (1) ns PRIEP3 tsu(EDIO_DATA_IN- EDC_SYNC_OUTx) Setup time, EDIO_DATA_IN valid before EDC_SYNC_OUTx active edge 20 ns PRIEP4 th(EDC_SYNC_OUTx- EDIO_DATA_IN) Hold time, EDIO_DATA_IN valid after EDC_SYNC_OUTx active edge 20 ns (1) P = PRU_ICSSG IEP clock source period in ns. EDC_SYNC_OUTx PRIEP4 PRIEP2 PRIEP3 EDIO_DATA_IN[7:0] PRU_IEP_TIMING_01 PRIEP1 Figure 7-94. PRU_ICSSG IEP SYNC Timing Requirements Table 7-95. PRU_ICSSG IEP Timing Requirements – Digital IOs see Figure 7-95 NO. PARAMETER DESCRIPTION MIN MAX UNIT IEPIO1 tw(EDIO_OUTVALIDL) Pulse duration, EDIO_OUTVALID low -2+14*P (1) ns IEPIO2 tw(EDIO_OUTVALIDH) Pulse duration, EDIO_OUTVALID high -2+32*P (1) ns IEPIO3 td(EDIO_OUTVALID- EDIO_DATA_OUT) Delay time, EDIO_OUTVALID to EDIO_DATA_OUT 0 18*P (1) ns IEPIO4 tsk(EDIO_DATA_OUT) EDIO_DATA_OUT skew 5 ns (1) P = PRU_ICSSG IEP clock source period in ns. EDIO_DATA_OUT PRU_EDIO_DATA_OUT_TIMING_00 IEPIO4 Figure 7-95. PRU_ICSSG IEP Digital IOs Timing Requirements Table 7-96. PRU_ICSSG IEP Timing Requirements – LATCH_INx see Figure 7-96 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRLA1 tw(EDC_LATCH_INxL) Pulse duration, EDC_LATCH_INx low 2+3*P (1) ns PRLA2 tw(EDC_LATCH_INxH) Pulse duration, EDC_LATCH_INx high 2+3*P (1) ns (1) P = PRU_ICSSG IEP clock source period in ns. AM6442, AM6441, AM6421 AM6412, AM6411 SPRSP56 – JANUARY 2021 www.ti.com 196 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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