AM6421 datasheet(193/237 Pages) TI

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a. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are INTEGERS -or- if PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an

EVEN INTEGER then, Y equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1). If PRUn_GPI_DIV0 is a NON-INTEGER and

PRUn_GPI_DIV1 is an ODD INTEGER then, Y equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 - 0.5).

b. If PRUn_GPI_DIV0 is an INTEGER and PRUn_GPI_DIV1 is a NON-INTEGER then, Y equals (PRUn_GPI_DIV0 *

PRUn_GPI_DIV1 - 0.5 * PRUn_GPI_DIV0).

c. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are NON-INTEGERS then, Y1 equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 - 0.25 *

PRUn_GPI_DIV0) and Y2 equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.25 * PRUn_GPI_DIV0), where Y1 is the first high

pulse and Y2 is the second high pulse.

CLOCKOUT

DATAOUT

PRSO1

PRSO2H

PRSO3

PRU_TIMING_06

PRSO2L

Figure 7-88. PRU_ICSSG PRU Shift Out Timing

7.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface

Table 7-87. PRU_ICSSG PRU Sigma Delta and Peripheral InterfaceTiming Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

V/ns

OUTPUT CONDITIONS

Output load capacitance

7.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing

Table 7-88. PRU_ICSSG PRU Timing Requirements – Sigma Delta Mode

see Figure 7-89 and Figure 7-90

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

PRSD1

tc(SD_CLK)

Cycle time, SDx_CLK

PRSD2L

tw(SD_CLKL)

Pulse duration, SDx_CLK low

PRSD2H

tw(SD_CLKH)

Pulse duration, SDx_CLK high

PRSD3

tsu(SD_D-SD_CLK)

Setup time, SDx_D valid before SDx_CLK active edge

PRSD4

th(SD_CLK-SD_D)

Hold time, SDx_D valid before SDx_CLK active edge

SDx_CLK

PRU_TIMING_07

PRSD2H

PRSD2L

PRSD4

PRSD3

SDx_D

PRSD1

Figure 7-89. PRU_ICSSG PRU SD_CLK Falling Active Edge

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SPRSP56 – JANUARY 2021

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