AM6421 datasheet(190/237 Pages) TI

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OSPI_CLK

OSPI_D[i:0]

OSPI_TIMING_05

O 9

O20

Figure 7-82. OSPI Timing Requirements – SDR, No Loopback Clock and Internal Pad Loopback Clock

OSPI_DQS

OSPI_TIMING_06

O21

O 2

OSPI_D[i:0]

Figure 7-83. OSPI Timing Requirements – SDR, External Loopback Clock

Table 7-81. OSPI DLL Delay Mapping for Timing Modes

MODE

OSPI_PHY_CONFIGURATION_REG BIT FIELD

DELAY VALUE

1.8V, OSPI0 DDR TX

PHY_CONFIG_TX_DLL_DELAY_FLD

0x45

3.3V, OSPI0 DDR TX

PHY_CONFIG_TX_DLL_DELAY_FLD

0x46

1.8V, OSPI0 DQS

PHY_CONFIG_RX_DLL_DELAY_FLD

0x14

3.3V, OSPI0 DQS

PHY_CONFIG_RX_DLL_DELAY_FLD

0x3A

All other modes

PHY_CONFIG_TX_DLL_DELAY_FLD,

PHY_CONFIG_RX_DLL_DELAY_FLD

0x0

7.10.5.15 PCIe

The PCI-Express Subsystem is compliant with the PCIe® Base Specification, Revision 4.0. Refer to the

specification for timing details.

For more details about features and additional description information on the device Peripheral Component

Interconnect Express, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8,

Detailed Description.

For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals

chapter in the device TRM.

7.10.5.16 PRU_ICSSG

The device has integrated two identical Programmable Real-Time Unit Subsystem and Industrial Communication

Subsystems - Gigabit (PRU_ICSSG), PRU_ICSSG0 and PRU_ICSSG1. The programmable nature of the PRU

cores, along with their access to pins, events and all device resources, provides flexibility in implementing fast

real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks

from the other processor cores in the device.

For more details about features and additional description information on the device PRU_ICSSG, see the

corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.

Note

The PRU_ICSSG0 and PRU_ICSSG1 support an internal wrapper multiplexing that expands the

device top-level multiplexing.

AM6442, AM6441, AM6421

AM6412, AM6411

SPRSP56 – JANUARY 2021

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