AM6421 datasheet(188/237 Pages) TI

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NO.(1) PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

O10 td(CLK-CSn)

Delay time, CLK rising edge to CSn active edge

1.8V

-1-0.475 * P –

0.975 * N * R

(3) (4) (5)

1-0.475 * P –

0.975 * N * R

(3) (4) (5)

3.3V

-1-0.475 * P –

0.975 * N * R

(3) (4) (5)

1-0.475 * P –

0.975 * N * R

(3) (4) (5)

O11 td(CLK-CSn)

Delay time, CLK rising edge to CSn inactive

edge

1.8V

-1+0.475 * P

+ 0.975 * N *

R (3) (4) (5)

1+0.475 * P +

0.975 * N * R

(3) (4) (5)

3.3V

-1+0.475 * P

+ 0.975 * N *

R (3) (4) (5)

1+0.475 * P +

0.975 * N * R

(3) (4) (5)

O12 td(CLK-D)

Delay time, CLK active edge to D[i:0] transition

1.8V

-1.15

1.25

3.3V

-1.33

1.51

(1)

i in [i:0] = 7 for OSPI0

(2)

P = CLK cycle time

(3)

P = SCLK period

(4)

N = OSPI_DEV_DELAY_REG[7-0] D_INIT_FLD

(5)

R = refclk

OSPI_CLK

OSPI_TIMING_02

OSPI_CSn

O10

O11

O12

OSPI_D[i:0]

Figure 7-79. OSPI Switching Characteristics – SDR

Section 7.10.5.14.2.3, Section 7.10.5.14.2.4, Figure 7-80, Figure 7-81, Figure 7-82, and Figure 7-83 presents

timing requirements for OSPI DDR and SDR Mode.

7.10.5.14.2.3 OSPI Timing Requirements – DDR Mode

NO.

(1)

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

O13 tsu(D-CLK)

Setup time, D[i:0] valid before active CLK edge

1.8V, No Loopback Clock; 1.8V,

Internal Pad Loopback Clock

5.23

3.3V, No Loopback Clock; 3.3V,

Internal Pad Loopback Clock

6.19

O14 th(CLK-D)

Hold time, D[i:0] valid after active CLK edge

1.8V, No Loopback Clock; 1.8V,

Internal Pad Loopback Clock

1.84

3.3V, No Loopback Clock; 3.3V,

Internal Pad Loopback Clock

2.34

O15 tsu(D-LBCLK)

Setup time, D[i:0] valid before active LBCLK (DQS)

edge

1.8V, External Board Loopback

Clock

0.52

3.3V, External Board Loopback

Clock

1.97

AM6442, AM6441, AM6421

AM6412, AM6411

SPRSP56 – JANUARY 2021

www.ti.com

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Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411

AM6421 Datasheet(PDF) 188 Page - Texas Instruments

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