AM6421 datasheet(189/237 Pages) TI

189 / 237 page

NO.

(1)

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

O16 th(LBCLK-D)

Hold time, D[i:0] valid after active LBCLK (DQS)

edge

1.8V, External Board Loopback

Clock

1.8 (2)

3.3V, External Board Loopback

Clock

2.2 (2)

O17 tsu(D-DQS)

Setup time, DQS edge to D[i:0] transition

1.8V, OSPI0 DQS;

-0.46

3.3V, OSPI0 DQS;

-0.66

O18 th(DQS-D)

Hold time, DQS edge to D[i:0] transition

1.8V, OSPI0 DQS;

3.59

3.3V, OSPI0 DQS;

7.92

(1)

i in [i:0] = 7 for OSPI0

(2)

This Hold time requirement is larger than the Hold time provided by a typical flash device. Therefore, the trace length between the SoC

and flash device must be sufficiently long enough to ensure that the Hold time is met at the SoC. The length of the SoC's external

loopback clock (OSPI_LBCLKO to OSPI_DQS) may need to be shortened to compensate.

OSPI_CLK

O14

O13

OSPI_TIMING_03

OSPI_D[i:0]

Figure 7-80. OSPI Timing Requirements – DDR, No Loopback Clock and Internal Pad Loopback Clock

OSPI_DQS

O16

O15

OSPI_TIMING_04

OSPI_D[i:0]

Figure 7-81. OSPI Timing Requirements – DDR, External Loopback Clock and DQS

7.10.5.14.2.4 OSPI Timing Requirements – SDR Mode

NO.

(1)

PARAMETE

DESCRIPTION

MODE

MIN

MAX

UNIT

O19 tsu(D-CLK)

Setup time, D[i:0] valid before active CLK

edge

1.8V, No Loopback Clock

-2.18

3.3V, No Loopback Clock

-1.7

O20 th(CLK-D)

Hold time, D[i:0] valid after active CLK edge

1.8V, No Loopback Clock

7.62

3.3V, No Loopback Clock

8.1

O21 tsu(D-LBCLK)

Setup time, D[i:0] valid before active LBCLK

input (DQS) edge

1.8V, External Board Loopback Clock

-3.24

3.3V, External Board Loopback Clock

-2.72

O22 th(LBCLK-D)

Hold time, D[i:0] valid after active LBCLK

input (DQS) edge

1.8V, External Board Loopback Clock

3.81

3.3V, External Board Loopback Clock

4.33

(1)

i in [i:0] = 7 for OSPI0

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AM6442, AM6441, AM6421

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SPRSP56 – JANUARY 2021

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Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411

AM6421 Datasheet(PDF) 189 Page - Texas Instruments

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