AM6421 datasheet(187/237 Pages) TI

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7.10.5.14.2.1 OSPI Switching Characteristics – DDR Mode

NO.(1) PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, CLK

1.8V

3.3V

tw(CLKL)

Pulse duration, CLK low

-0.3+0.475*P

(2)

tw(CLKH)

Pulse duration, CLK high

-0.3+0.475*P

(2)

td(CLK-CSn)

Delay time, CLK rising edge to CSn active edge

1.8V, OSPI0 DDR TX; -7.7-0.475 * P

– 0.975 * N *

R (3) (4) (5)

0-0.475 * P –

0.975 * N * R

(3) (4) (5)

3.3V, OSPI0 DDR TX; -8-0.475 * P –

0.975 * N * R

(3) (4) (5)

0-0.475 * P –

0.975 * N * R

(3) (4) (5)

td(CLK-CSn)

Delay time, CLK rising edge to CSn inactive

edge

1.8V, OSPI0 DDR TX;

-7.7+0.475 *

P + 0.975 * N

* R (3) (4) (5)

0+0.475 * P +

0.975 * N * R

(3) (4) (5)

3.3V, OSPI0 DDR TX;

-8+0.475 * P

+ 0.975 * N *

R (3) (4) (5)

0+0.475 * P +

0.975 * N * R

(3) (4) (5)

td(CLK-D)

Delay time, CLK active edge to D[i:0] transition

1.8V, OSPI0 DDR TX;

-7.7

-1.56

3.3V, OSPI0 DDR TX;

-7.7

-1.56

(1)

i in [i:0] = 7 for OSPI0

(2)

P = CLK cycle time

(3)

P = SCLK period

(4)

N = OSPI_DEV_DELAY_REG[7-0] D_INIT_FLD

(5)

R = refclk

OSPI_CLK

OSPI_TIMING_01

OSPI_CSn

OSPI_D[i:0]

Figure 7-78. OSPI Switching Characteristics – DDR

7.10.5.14.2.2 OSPI Switching Characteristics – SDR Mode

NO.(1) PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, CLK

1.8V

3.3V

7.52

tw(CLKL)

Pulse duration, CLK low

-0.3+0.475*P

(2)

tw(CLKH)

Pulse duration, CLK high

-0.3+0.475*P

(2)

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AM6442, AM6441, AM6421

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SPRSP56 – JANUARY 2021

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