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AM6421 Datasheet(PDF) 183 Page - Texas Instruments |
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AM6421 Datasheet(HTML) 183 Page - Texas Instruments |
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183 / 237 page  MMCi_CLK MMCi_CMD MMCi_DAT[j:0] SDR251 SDR252L SDR252H HSSDR255 SDR256 SDR255 SDR256 MMC1_08 Figure 7-71. MMC1 – UHS-I SDR25 – Transmit Mode 7.10.5.12.2.5 UHS–I SDR50 Mode , Table 7-74, and Figure 7-72 presents switching characteristics for MMC1 – UHS-I SDR50 Mode. Table 7-74. Switching Characteristics for MMC1 – UHS-I SDR50 Mode see Figure 7-72 NO. PARAMETER DESCRIPTION MIN MAX UNIT fop(clk) Operating frequency, MMC1_CLK 100 MHz SDR501 tc(clk) Cycle time, MMC1_CLK 10 ns SDR502H tw(clkH) Pulse duration, MMC1_CLK high 4.45 ns SDR502L tw(clkL) Pulse duration, MMC1_CLK low 4.45 ns SDR505 td(clkL-cmdV) Delay time, MMC1_CLK rising edge to MMC1_CMD transition 1.2 6.35 ns SDR506 td(clkL-dV) Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition 1.2 6.35 ns MMCi_CLK MMCi_CMD MMCi_DAT[j:0] SDR501 SDR502L SDR502H SDR505 SDR506 SDR505 SDR506 MMC1_10 Figure 7-72. MMC1 – UHS-I SDR50 – Transmit Mode 7.10.5.12.2.6 UHS–I DDR50 Mode Table 7-75, Figure 7-73, Table 7-76, and Figure 7-74 present timing requirements and switching characteristics for MMC1 – UHS-I DDR50 Mode. Table 7-75. Timing Requirements for MMC1 – UHS-I DDR50 Mode see Figure 7-73 NO. PARAMETER DESCRIPTION MIN MAX UNIT DDR505 tsu(cmdV-clk) Setup time, MMC1_CMD valid before MMC1_CLK rising edge 2.99 ns DDR506 th(clk-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising edge 1.91 ns DDR507 tsu(dV-clk) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK transition -0.06 ns DDR508 th(clk-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK transition 1.91 ns www.ti.com AM6442, AM6441, AM6421 AM6412, AM6411 SPRSP56 – JANUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 183 Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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