LAN7430 datasheet(19/77 Pages) MICROCHIP

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DS00002631D-page 19

LAN7430/LAN7431

Receive Error

RX_ER

VIS

Asserted to indicate an error has been detected in the

frame presently being transferred from the external

Ethernet PHY.

Receive Clock

RX_CLK

VIS

Used to transfer data from the external Ethernet PHY to

the MAC in MII mode.

100BASE-TX: 25MHz

10BASE-T: 2.5MHz

25 MHz Refer-

ence Clock

REFCLK_25

VO12

25 MHz reference clock to be provided to and used as a

reference by the external Fast Ethernet PHY.

PHY Interrupt

PHY_INT_N

VIS

Interrupt from external Ethernet PHY.

PHY Reset

PHY_RESET_N

VO12

Reset to external Ethernet PHY.

Duplex Mode

DUPLEX

VIS

Duplex Mode. This signal connects to the Duplex Mode

output from external Ethernet PHY.

When set the external Ethernet PHY is in Full Duplex

mode.

Note:

If the external Ethernet PHY does not have a

duplex output signal, then it is recommended

that this signal should be tied to VDDVARIO to

force full duplex operation

Management

Interface Data

MDIO

VIS/

VO8

(PU)

This is the management data to/from an external Ether-

net PHY.

Note:

An external pull-up is required when the MII

management interface is used, to ensure that

the IDLE state of the MDIO signal is a logic

one.

Note:

An external pull-up is recommended when the

MII management interface is not used, to avoid

a floating signal.

APPLICATION NOTE:

A pull-up (internal or external)

will result in a return value of

FFFFh when a non-existent or

non-addressed PHY is read. If a

value of 0000h is desired

instead, a pull-down may be

used.

Management

Interface Clock

MDC

VO8

This is the management clock output to an external

Ethernet PHY

PCIe

TX Positive

PCIE_TX_P

PCIe Serial Data Output positive.

Serial differential output link in the PCIe interface running

at 2.5 GT/s.

A series capacitor in the range of 100nF to 200nF is

required.

TABLE 3-3:

PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Buffer

Type

Description

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