LAN7430 datasheet(23/77 Pages) MICROCHIP

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DS00002631D-page 23

LAN7430/LAN7431

Configuration Straps

MII Enable

Configuration

Strap

MII_EN

VIS

(PD)

(LAN7431 only)

When pulled high, the port operates in MII mode. When

pulled low or floated, the port operates in RGMII mode.

See Section 3.4, "Configuration Straps" for additional

information.

Note:

The internal pull-down is disabled once the

strap is latched.

Note:

If an external pull-up is used, it should be

connected to VDDVARIO_B.

Advance Power

Management Dis-

able

Configuration

Strap

ADV_PM_DISABLE

VIS

(PD)

When pulled high, the following bits default low. When

pulled low or floated, the register bits default high.

• Clock Power Management in Link Capabilities

• L1 PM Substates Supported in L1 PM Substates

Capabilities

• ASPM L1.1 Supported in L1 PM Substates Capabili-

ties

• ASPM L1.2 Supported in L1 PM Substates Capabili-

ties

• PCI-PM L1.1 Supported in L1 PM Substates Capa-

bilities

• PCI-PM L1.2 Supported in L1 PM Substates Capa-

bilities

Note:

Regardless of the strap default, the bits may be

loaded from OTP or EEPROM. The default is

used in the absence of a programmed OTP or

EEPROM.

Note:

The internal pull-down is disabled once the

strap is latched.

Note:

If an external pull-up is used, it should be

connected to VDDVARIO.

Power / Ground

Ethernet PHY

+1.2V Analog

Power Supply

AVDD12

1.2V power for PLL/DLL

Ethernet PHY

+2.5V / 3.3V Ana-

log Power Supply

AVDDH_1

2.5V or 3.3V power for analog IO

LAN7430 only

This pin provides power for Gigabit PHY transmitter,

bandgap reference, and crystal oscillator amplifier.

LAN7431 only

This pin provides power for bandgap reference and crys-

tal oscillator amplifier.

Ethernet PHY

+2.5V / 3.3V Ana-

log Power Supply

AVDDH_2

2.5V or 3.3V power for analog IO

(LAN7430 only)

This pin provides power for Gigabit PHY transmitter.

TABLE 3-3:

PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Buffer

Type

Description

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