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LAN7430 Datasheet(PDF) 67 Page - Microchip Technology |
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LAN7430 Datasheet(HTML) 67 Page - Microchip Technology |
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67 / 77 page  2018-2019 Microchip Technology Inc. DS00002631D-page 67 LAN7430/LAN7431 7.6.9 EEPROM TIMING FIGURE 7-14: EEPROM TIMING TABLE 7-22: EEPROM TIMING VALUES Symbol Description Min Typ Max Units tckcyc EECLK Cycle time 1110 1130 ns tckh EECLK High time 550 570 ns tckl EECLK Low time 550 570 ns tcshckh EECS high before rising edge of EECLK 1070 ns tcklcsl EECLK falling edge to EECS low 30 ns tdvckh EEDIO valid before rising edge of EECLK 550 ns tckhinvld EEDIO invalid after rising edge EECLK 550 ns tdsckh EEDIO setup to rising edge of EECLK 90 ns tdhckh EEDIO hold after rising edge of EECLK 0 ns tckldis EECLK low to data disable (OUTPUT) 580 ns tcshdv EEDIO valid after EECS high (VERIFY) 600 ns tdhcsl EEDIO hold after EECS low (VERIFY) 0 ns tcsl EECS low 1070 ns EECLK EEDIO (output) EEDIO (input) EECS tckldis tcshckh EEDIO (input) (VERIFY) tckh tckl tckcyc tcklcsl tcsl tdvckh tckhinvld tdsckh tdhckh tdhcsl tcshdv |
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