LAN7430 datasheet(45/77 Pages) MICROCHIP

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DS00002631D-page 45

LAN7430/LAN7431

L1 PM Sub-states

– optional L1.1 and L1.2 sub-states of the L1 low power Link state for PCI-PM and ASPM are sup-

ported by the device.

L1.0 Sub-state

This sub-state corresponds to the conventional L1 Link state, when L1 PM Sub-states are enabled by setting one or

more of the enable bits in the PCIe L1 PM Substates Control 1 configuration register but the device is not in either of

those sub-states.

This sub-state is entered whenever the Link enters L1.

The port is required to be enabled to detect Electrical Idle and the Link common mode voltages are maintained.

L1.1 Sub-state

The port is not required to be enabled to detect Electrical Idle but the Link common mode voltages are maintained.

The bidirectional open-drain clock request (CLKREQ#) signal controls entry and exit from this state. After the link has

entered L1 through the normal L1 negotiation, the device can initiate the sequence for entering L1.1 by three-stating the

CLKREQ# output buffer. The entry sequence can only proceed if the DSP is also three-stating its CLKREQ# output buf-

fer, resulting in the bidirectional CLKREQ# signal being pulled up to 1. Otherwise CLKREQ# will remain asserted at 0

and the link state will stay in L1.0.

The exit sequence can be initiated by either port by asserting CLKREQ# to 0.

L1.2 Sub-state

The port is not required to be enabled to detect Electrical Idle nor maintain the Link common mode voltages.

The bidirectional open-drain clock request (CLKREQ#) signal controls entry and exit from this state. After the link has

entered L1 through the normal L1 negotiation, the device can initiate the sequence for entering L1.2 by three-stating the

CLKREQ# output buffer. The entry sequence can only proceed if the DSP is also three-stating its CLKREQ# output buf-

fer, resulting in the bidirectional CLKREQ# signal being pulled up to 1. Otherwise CLKREQ# will remain asserted at 0

and the link state will stay in L1.0.

The exit sequence can be initiated by either port by asserting CLKREQ# to 0.

L1.2 is further subdivided into L1.2.Entry, L1.2.Idle and L1.2.Exit.

Table 6-2 details the various L1 sub-state exit latencies.

6.13.3

LATENCY TOLERANCE REPORTING (LTR) MECHANISM

The Latency Tolerance Reporting (LTR) mechanism enables the endpoint to report the service latency requirements for

Memory Reads and Writes to the Root Complex. Power management policies for central platform resources (such as

main memory, RC internal interconnects, and snoop resources) can be implemented to consider the endpoint service

requirements. The Root Complex is not required to honor the requested service latencies, but is strongly encouraged

to provide a worst case service latency that does not exceed the latencies indicated by the LTR mechanism.

This device supports LTR as indicated by the LTR Mechanism Supported bit in the PCIe Device Capabilities 2 configu-

ration register. LTR is enabled via the LTR Mechanism Enable bit in the PCIe Device Control 2 configuration register.

The LTR mechanism tells the host the latency tolerance the device has in response to a request from the device. This

allows the host to judiciously decide how long to wait before servicing the interrupt from the device. System power con-

sumption is optimized by enabling the Host CPU and memory sub-system to utilize the device’s latency, and power

down and stay in their low power states longer.

TABLE 6-2:

L1 SUB-STATE EXIT LATENCIES

L1 Sub-state

Exit Latency (uS)

L1 with CLKREQ# (CPM)

<68

L1.1

<68

L1.2

<88

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