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ADRV9029BBCZ Datasheet(PDF) 3 Page - Analog Devices

Part # ADRV9029BBCZ
Description  Integrated, Quad RF Transceiver with Observation Path
PDF  133 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADRV9029BBCZ Datasheet(HTML) 3 Page - Analog Devices

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Data Sheet
ADRV9029
Rev. 0 | Page 3 of 133
FUNCTIONAL BLOCK DIAGRAM
SERDOUTA±
SERDOUTB±
SYNCOUT1±
SYNCOUT2±
ORX_CTRL_x
RXx_EN
GPINT2
GPINT1
TXx_EN
RESET
TEST_EN
SPI_DIO
SPI_DO
SPI_EN
SPI_CLK
SYSREF±
DEVCLK±
GPIO_x
AUXADC_x
GPIO_ANA_x
JESD204B/
JESD204C
SERIAL
INTERFACE
RX1+
RX1–
RX2+
RX2–
RX3+
RX3–
RX4+
RX4–
ADC
ADC
Rx1
Rx2
RX1, RX2, TX1, TX2, ORX1/ORX2
RX3, RX4, TX3, TX4, ORX3/ORX4
0°
90°
LO 1
LO 2
LO 1
LO 2
LO 3
DECIMATION,
pFIR,
AGC,
DC-OFFSET,
QEC,
TUNING,
RSSI,
OVERLOAD
TX1+
TX1–
TX2+
TX2–
TX3+
TX3–
TX4+
TX4–
DAC
DAC
Tx1
Tx2
pFIR,
LO LEAKAGE,
QEC,
TUNING,
INTERPOLATION
CFR
DPD
ORX1+
ORX1–
ORX2+
ORX2–
ORX3+
ORX3–
ORX4+
ORX4–
VIF
VDIG_1P0
EXT_LO1±
EXT_LO2±
VDDA_1P32
VDDA_1P03
VDDA_1P81
ADC
ADC
ORx1/ORx2
DECIMATION,
pFIR,
DC-OFFSET,
QEC,
TUNING,
OVERLOAD
POWER
MANAGEMENT
CLOCK GENERATION
AND
SYNCHRONIZATION
GPIO
AUXILIARY ADC
AUXILIARY DAC
SPI PORT
CONTROL
INTERFACE
RF SYNTHESIZER
LO 3
MICROPROCESSOR
SERDOUTC±
SERDOUTD±
SYNCIN1±
SYNCIN2±
SYNCIN3±
SERDINA±
SERDINB±
SERDINC±
SERDIND±
8
4
4
4
4
19
RF SYNTHESIZER
RF SYNTHESIZER
LO 1
LO 2
1VDDA_1P8 REPRESENTS VCONV1_1P8, VCONV2_1P8, VANA1_1P8, VANA2_1P8, VANA3_1P8, VANA4_1P8, AND VJVCO_1P8.
2VDDA_1P3 REPRESENTS VANA1_1P3, VANA2_1P3, VCONV1_1P3, VCONV2_1P3, VRFVCO1_1P3, VRFVCO2_1P3, VAUXVCO_1P3, VCLKVCO_1P3,
VRFSYN1_1P3, VRFSYN2_1P3, VCLKSYN_1P3, VAUXSYN_1P3, VRXLO_1P3, AND VTXLO_1P3.
3VDDA_1P0 REPRESENTS VJSYN_1P0, VDES_1P0, VTT_DES, AND VSER_1P0.
0°
90°
0°
90°
ADRV9029
Figure 1.



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