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ADRV9029BBCZ Datasheet(PDF) 17 Page - Analog Devices |
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ADRV9029BBCZ Datasheet(HTML) 17 Page - Analog Devices |
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17 / 133 page  Data Sheet ADRV9029 Rev. 0 | Page 17 of 133 DIGITAL INTERFACE AND TIMING SPECIFICATIONS Table 8. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SERIAL PERIPHERAL INTERFACE (SPI) TIMING SPI_CLK Period tCP 40 ns SPI_CLK Pulse Width tMP 10 ns SPI_EN Setup to First SPI_CLK Rising Edge tSC 4 ns Last SPI_CLK Falling Edge to SPI_EN Hold tHC 0 ns SPI_DIO Data Input Setup to SPI_CLK tS 4 ns SPI_DIO Data Input Hold to SPI_CLK tH 0 ns SPI_CLK Falling Edge to Output Data Delay tCO 10 8 ns 3- or 4-wire mode Bus Turnaround Time After Baseband Processor Drives Last Address Bit tHZM tH tCO ns Bus Turnaround Time After ADRV9029 Drives Last Address Bit tHZS 0 tCO ns DIGITAL TIMING TXx_EN Pulse Width 10 μs RXx_EN Pulse Width 10 μs ORX_CTRL_x Pulse Width 10 μs TXx_EN to Valid Data 2 μs RXx_EN to Valid Data 2 μs ORX_CTRL_x to Valid Data 3 μs JESD204B/JESD204C DATA OUTPUT TIMING Unit Interval UI 41.1 333 ps Data Rate per Channel (No Return to Zero (NRZ)) 3000 24330.24 Mbps Rise Time tR 17 20 ps 20% to 80% in 100 Ω load Fall Time tF 17 20 ps 20% to 80% in 100 Ω load Output Common-Mode Voltage VCM 0 1.8 V AC-coupled Differential Output Voltage VDIFF 475 1050 mV p-p Short-Circuit Current IDSHORT −100 +100 mA Differential Termination Impedance ZRDIFF 80 100 120 Ω SYSREF± Input Signal Setup Time to DEV_CLK± Input Signal tS 200 ps SYSREF± Input Signal Hold Time to DEV_CLK± Input Signal tH 200 ps JESD204B/C DATA INPUT TIMING Unit Interval UI 41.1 333 ps Data Rate per Channel (NRZ) 3000 24330.24 Mbps Input Common-Mode Voltage VCM 0.05 1.65 V AC-coupled Termination Voltage = 1.0 V VTT 720 1200 mV DC-coupled (not recommended) Differential Input Voltage VDIFF 110 1050 mV VTT Source Impedance ZTT 7.5 30 Ω Differential Termination Impedance ZRDIFF 80 100 120 Ω VTT AC-Coupled 0.95 1.05 V DC-Coupled 0.95 1.05 V |
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