K32L2AX datasheet(23/96 Pages) NXP

23 / 96 page

The module can remain functional in VLPS mode provided the clock it is using

remains enabled.

2.2.16 Peripheral Clock Control (PCC)

The device deploys two Peripheral Clock Control modules that allow clock gating,

and clock source selection to each peripheral. Each AIPS bridge has its own

corresponding PCC module. In addition to this clock, there are optional peripheral

clock sources that may be asynchronous to the CPU/Platform clock: SCGIRCLK,

SCGFIRCLK, SCGPCLK, SCGFCLK, LPO, OSCCLK, SCGSPCLK.

2.2.17 Real Time Clock (RTC)

The RTC module features include:

• 32-bit seconds counter with roll-over protection and 32-bit alarm

• 16-bit prescaler with compensation that can correct errors between 0.12 ppm and

3906 ppm

• Option to increment prescaler using the LPO (prescaler increments by 32 every

clock edge)

• Register write protection

• Lock register requires POR or software reset to enable write access

• Configurable 1, 2, 4, 8, 16, 32, 64 or 128 Hz square wave output with optional

interrupt

The device has one secure RTC. The RTC module is accessed via AIPS0 peripheral

bridge.

2.2.18 Timer/PWM Module (TPM)

The TPM (Timer/PWM Module) is a 2- to 8-channel timer which supports input

capture, output compare, and the generation of PWM signals to control electric motor

and power management applications.

This device contains 3 low-power Timer/PWM modules (TPM), which can all be

functional in Stop/VLPS mode. In Stop/VLPS mode, the clock source is either

external or internal.

Overview

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

K32L2AX Datasheet(PDF) 23 Page - NXP Semiconductors