K32L2AX datasheet(82/96 Pages) NXP

82 / 96 page

Table 51. LPSPI slave mode timing on slew rate enabled pads

Num.

Symbol

Description

Min.

Max.

Unit

Note

fop

Frequency of operation

fperiph/4

tSPSCK

SPSCK period

4 x tperiph

—

tLead

Enable lead time

—

tperiph

—

tLag

Enable lag time

—

tperiph

—

tWSPSCK

Clock (SPSCK) high or low time

tperiph - 30

—

tSU

Data setup time (inputs)

—

tHI

Data hold time (inputs)

—

Slave access time

—

tperiph

tdis

Slave MISO disable time

—

tperiph

Data valid (after SPSCK edge)

—

122

—

tHO

Data hold time (outputs)

—

tRI

Rise time input

—

tperiph - 25

—

tFI

Fall time input

tRO

Rise time output

—

tFO

Fall time output

1. fperiph is the LPSPI peripheral functional clock

2. tperiph = 1/fperiph

3. Time to data active from high-impedance state

4. Hold time to high-impedance state

MSB IN

BIT 6 . . . 1

SLAVE MSB

SLAVE LSB OUT

NOTE: Not defined

SEE

NOTE

see

note

(INPUT)

(CPOL=0)

SPSCK

(CPOL=1)

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

LSB IN

BIT 6 . . . 1

Figure 24. LPSPI slave mode timing (CPHA = 0)

Peripheral operating requirements and behaviors

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

K32L2AX Datasheet(PDF) 82 Page - NXP Semiconductors

K32L2AX Datasheet(HTML) 82 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL