EDSTRG28PLCCCX datasheet(34/78 Pages) TI

34 / 78 page

TIMING CONVENTIONS

1–26

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delay time

The time interval between two signals identified in the description column of the following example symbology.

Example symbology:

Classified

Description

td(CIH-SCL)

Delay time, XTAL2 / CLKIN rise to SYSCLK fall

td(CIH-SCH)

Delay time, XTAL2 / CLKIN rise to SYSCLK rise

td(SCL-A)

Delay time, SYSCLK low to address R / W and OCF valid

td(DZ-EL)

Delay time, data bus high impedance to EDS low (read cycle)

td(EH-D)

Delay time, EDS high to data bus enable (read cycle)

td(EL-DV)R

Delay time, EDS low to read data valid

td(EL-WTV)

Delay time, EDS low to WAIT valid

td(AV-DV)R

Delay time, address valid to read data valid

td(AV-WTV)

Delay time, address valid to WAIT valid

td(AV-EH)

Delay time, address valid to EDS high (end of write)

td(SCCL-TXDV)

Delay time, SCITXD valid after SCICLK low

td(SPCL-SIMOV)

Delay time, SPISIMO valid after SPICLK low (polarity = 1)

td(SPCL-SOMIV)

Delay time, SPISOMI valid after SPICLK low (polarity = 1)

timing-diagram conventions

State unknown or changing

Will be changing from low to high sometime

during designated intervals

Will be changing from high to low sometime

during designated intervals

Will be steady high or low

Don’t care

Low-to-high changes permitted

High-to-low changes permitted

Must be steady high or low

Meaning

Output Response Functions

Input Forcing Functions

Timing-Diagram Symbol

EDSTRG28PLCCCX Datasheet(PDF) 34 Page - Texas Instruments

EDSTRG28PLCCCX Datasheet(HTML) 34 Page - Texas Instruments

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