EDSTRG28PLCCCX datasheet(45/78 Pages) TI

45 / 78 page

GLOSSARY/SYMBOLS, TERMS, AND DEFINITIONS

1–37

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WAIT pin:

The pin that allows an external device to cause the processor to wait (holding the information on the ex-

pansion bus) for an indefinite number of clock cycles (one or more extra clockout cycles). When the wait line is

released, the processor resynchronizes with the rising edge of the clockout signal (CLKOUT) after EDS goes ac-

tive and continues with the program.

wait states, automatic:

Extra clock cycles inserted automatically on every external-memory access to accommo-

date peripherals or expansion memory with slower access time than the TMS370 processor. These wait states

are governed by two control bits: PF AUTOWAIT (SCCR0.5) and AUTOWAIT DISABLE (SCCR1.4).

watchdog (WD) timer:

A timer option that can be programmed to generate an interrupt when it times out. This func-

tion serves as a hardware monitor over the software to prevent a “lost” program and is available in both the

timer 1 and PACT modules. If timer 1 does not need a watchdog, this timer can be used as a general-purpose

timer.

write:

A memory operation whereby data is written into a desired address location

Write Enable:

A control signal that when true causes the memory to assume the write mode, and when false causes

it to assume the read mode

write-protect override (WPO):

The only mode in which a TMS370 device can modify the on-board EEPROM. The

WPO mode is entered when external circuitry applies 12 V to the MC pin after the device has been reset into one

of its normal operating modes.

XDS/22:

A code-development tool that is external to the target system and provides direct control over the TMS370

processor that is on the target system

EDSTRG28PLCCCX Datasheet(PDF) 45 Page - Texas Instruments