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EDSTRG28PLCCCX Datasheet(PDF) 20 Page - Texas Instruments |
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EDSTRG28PLCCCX Datasheet(HTML) 20 Page - Texas Instruments |
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20 / 78 page ![]() FUNCTIONAL-BLOCK-DIAGRAM GENERALIZATION 1–12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional-block-diagram generalization (continued) Interrupts System Control Clock Options Divide-by-4 or Divide-by-1(PLL) Serial Peripheral Interface† Program Memory ROM: 2K, 4K, 8K, 12K, 16K, 24K, 32K or 48K Bytes† EPROM: 8K, 16K, 24K, 32K or 48K Bytes† Watchdog Timer 1† Serial Communications Interface† Timer 2A† Timer 2B† PACT† Mini SCI Watchdog 128 Bytes Dual-Port RAM† Data EEPROM 256 or 512 Bytes† RAM 128, 256, 384, 512, 1K or 3.5K Bytes† CPU VSS2† VCC2† VCC1 VSS1 1 8 8 8 8 SCIRXD SCITXD OP8 OP1 CP6 CP1 T1PWM T1EVT T1IC / CR T2AIC2 / PWM T2AEVT T2AIC1 / CR T2BIC2 / PWM T2BEVT T2BIC1 / CR SCICLK SCITXD SCIRXD SPICLK SPISIMO SPISOMI 8 Port APort B † Port C † Port DPort G † Port H † VSS3 VCC3 Standby RAM 256 Bytes† Memory Expansion† VCCSTBY INT1 INT2 INT3 XTAL1 XTAL2 / CLKIN MC RESET E0 – E7 or AN0 – AN7 Analog-to-Digital Converter† † Not available on all devices; see the selection reference guide (Table 4). |
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